cfg->regtype = SCIx_HSCIF_REGTYPE;
break;
default:
- printk(KERN_ERR "Can't probe register map for given port\n");
+ pr_err("Can't probe register map for given port\n");
return -EINVAL;
}
if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
copied++;
- dev_notice(port->dev, "overrun error");
+ dev_notice(port->dev, "overrun error\n");
}
if (status & SCxSR_FER(port)) {
if (tty_insert_flip_char(tport, 0, TTY_PARITY))
copied++;
- dev_notice(port->dev, "parity error");
+ dev_notice(port->dev, "parity error\n");
}
if (copied)
/* Disable future Rx interrupts */
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
disable_irq_nosync(irq);
- scr |= 0x4000;
+ scr |= SCSCR_RDRQE;
} else {
scr &= ~SCSCR_RIE;
}
sci_port = container_of(self, struct sci_port, freq_transition);
- if ((phase == CPUFREQ_POSTCHANGE) ||
- (phase == CPUFREQ_RESUMECHANGE)) {
+ if (phase == CPUFREQ_POSTCHANGE) {
struct uart_port *port = &sci_port->port;
spin_lock_irqsave(&port->lock, flags);
*/
reg = sci_getreg(port, SCFCR);
if (reg->size)
- serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
+ serial_port_out(port, SCFCR,
+ serial_port_in(port, SCFCR) |
+ SCFCR_LOOP);
}
}
unsigned long flags;
int count;
- dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
+ dev_dbg(port->dev, "%s(%d) active #%d\n",
+ __func__, port->line, s->active_rx);
spin_lock_irqsave(&port->lock, flags);
sci_rx_dma_release(s, true);
return;
}
- dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
- s->cookie_rx[i], i);
+ dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
+ __func__, s->cookie_rx[i], i);
}
s->active_rx = s->cookie_rx[0];
unsigned long flags;
int count;
- chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+ dmaengine_terminate_all(chan);
dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
sh_desc->partial, sh_desc->cookie);
s->active_rx = s->cookie_rx[!new];
- dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
- s->cookie_rx[new], new, s->active_rx);
+ dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
+ __func__, s->cookie_rx[new], new, s->active_rx);
}
static void work_fn_tx(struct work_struct *work)
return;
}
- dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
- xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
+ dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
+ __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
dma_async_issue_pending(chan);
}
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 new, scr = serial_port_in(port, SCSCR);
if (s->chan_tx)
- new = scr | 0x8000;
+ new = scr | SCSCR_TDRQE;
else
- new = scr & ~0x8000;
+ new = scr & ~SCSCR_TDRQE;
if (new != scr)
serial_port_out(port, SCSCR, new);
}
ctrl = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
- ctrl &= ~0x8000;
+ ctrl &= ~SCSCR_TDRQE;
ctrl &= ~SCSCR_TIE;
ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
- ctrl &= ~0x4000;
+ ctrl &= ~SCSCR_RDRQE;
serial_port_out(port, SCSCR, ctrl);
}
ctrl = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
- ctrl &= ~0x4000;
+ ctrl &= ~SCSCR_RDRQE;
ctrl &= ~port_rx_irq_mask(port);
{
struct sh_dmae_slave *param = slave;
- dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
- param->shdma_slave.slave_id);
+ dev_dbg(chan->device->dev, "%s: slave ID %d\n",
+ __func__, param->shdma_slave.slave_id);
chan->private = ¶m->shdma_slave;
return true;
u16 scr = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
- scr &= ~0x4000;
+ scr &= ~SCSCR_RDRQE;
enable_irq(s->irqs[SCIx_RXI_IRQ]);
}
serial_port_out(port, SCSCR, scr | SCSCR_RIE);
dma_cap_mask_t mask;
int nent;
- dev_dbg(port->dev, "%s: port %d\n", __func__,
- port->line);
+ dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
return;
if (!nent)
sci_tx_dma_release(s, false);
else
- dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
+ dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
+ __func__,
sg_dma_len(&s->sg_tx), port->state->xmit.buf,
&sg_dma_address(&s->sg_tx));
return ((freq + 16 * bps) / (32 * bps) - 1);
}
+/* calculate frame length from SMR */
+static int sci_baud_calc_frame_len(unsigned int smr_val)
+{
+ int len = 10;
+
+ if (smr_val & SCSMR_CHR)
+ len--;
+ if (smr_val & SCSMR_PE)
+ len++;
+ if (smr_val & SCSMR_STOP)
+ len++;
+
+ return len;
+}
+
+
/* calculate sample rate, BRR, and clock select for HSCIF */
static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
int *brr, unsigned int *srr,
- unsigned int *cks)
+ unsigned int *cks, int frame_len)
{
- int sr, c, br, err;
+ int sr, c, br, err, recv_margin;
int min_err = 1000; /* 100% */
+ int recv_max_margin = 0;
/* Find the combination of sample rate and clock select with the
smallest deviation from the desired baud rate. */
for (sr = 8; sr <= 32; sr++) {
for (c = 0; c <= 3; c++) {
/* integerized formulas from HSCIF documentation */
- br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
- if (br < 0 || br > 255)
+ br = DIV_ROUND_CLOSEST(freq, (sr *
+ (1 << (2 * c + 1)) * bps)) - 1;
+ br = clamp(br, 0, 255);
+ err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
+ (1 << (2 * c + 1)) / 1000)) -
+ 1000;
+ if (err < 0)
continue;
- err = freq / ((br + 1) * bps * sr *
- (1 << (2 * c + 1)) / 1000) - 1000;
+
+ /* Calc recv margin
+ * M: Receive margin (%)
+ * N: Ratio of bit rate to clock (N = sampling rate)
+ * D: Clock duty (D = 0 to 1.0)
+ * L: Frame length (L = 9 to 12)
+ * F: Absolute value of clock frequency deviation
+ *
+ * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
+ * (|D - 0.5| / N * (1 + F))|
+ * NOTE: Usually, treat D for 0.5, F is 0 by this
+ * calculation.
+ */
+ recv_margin = abs((500 -
+ DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
if (min_err > err) {
min_err = err;
- *brr = br;
- *srr = sr - 1;
- *cks = c;
- }
+ recv_max_margin = recv_margin;
+ } else if ((min_err == err) &&
+ (recv_margin > recv_max_margin))
+ recv_max_margin = recv_margin;
+ else
+ continue;
+
+ *brr = br;
+ *srr = sr - 1;
+ *cks = c;
}
}
{
struct sci_port *s = to_sci_port(port);
struct plat_sci_reg *reg;
- unsigned int baud, smr_val, max_baud, cks = 0;
+ unsigned int baud, smr_val = 0, max_baud, cks = 0;
int t = -1;
unsigned int srr = 15;
+ if ((termios->c_cflag & CSIZE) == CS7)
+ smr_val |= SCSMR_CHR;
+ if (termios->c_cflag & PARENB)
+ smr_val |= SCSMR_PE;
+ if (termios->c_cflag & PARODD)
+ smr_val |= SCSMR_PE | SCSMR_ODD;
+ if (termios->c_cflag & CSTOPB)
+ smr_val |= SCSMR_STOP;
+
/*
* earlyprintk comes here early on with port->uartclk set to zero.
* the clock framework is not up and running at this point so here
baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
if (likely(baud && port->uartclk)) {
if (s->cfg->type == PORT_HSCIF) {
+ int frame_len = sci_baud_calc_frame_len(smr_val);
sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
- &cks);
+ &cks, frame_len);
} else {
t = sci_scbrr_calc(s, baud, port->uartclk);
for (cks = 0; t >= 256 && cks <= 3; cks++)
sci_reset(port);
- smr_val = serial_port_in(port, SCSMR) & 3;
-
- if ((termios->c_cflag & CSIZE) == CS7)
- smr_val |= 0x40;
- if (termios->c_cflag & PARENB)
- smr_val |= 0x20;
- if (termios->c_cflag & PARODD)
- smr_val |= 0x30;
- if (termios->c_cflag & CSTOPB)
- smr_val |= 0x08;
+ smr_val |= serial_port_in(port, SCSMR) & 3;
uart_update_timeout(port, termios->c_cflag, baud);
__func__, smr_val, cks, t, s->cfg->scscr);
if (t >= 0) {
- serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
+ serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
serial_port_out(port, SCBRR, t);
reg = sci_getreg(port, HSSRR);
if (reg->size)
if (s->chan_rx) {
s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
port->fifosize / 2;
- dev_dbg(port->dev,
- "DMA Rx t-out %ums, tty t-out %u jiffies\n",
+ dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
s->rx_timeout * 1000 / HZ, port->timeout);
if (s->rx_timeout < msecs_to_jiffies(20))
s->rx_timeout = msecs_to_jiffies(20);
struct sci_port *sci_port = to_sci_port(port);
switch (state) {
- case 3:
+ case UART_PM_STATE_OFF:
sci_port_disable(sci_port);
break;
default:
* need to do any remapping, just cast the cookie
* directly.
*/
- port->membase = (void __iomem *)port->mapbase;
+ port->membase = (void __iomem *)(uintptr_t)port->mapbase;
}
return 0;
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
-static char banner[] __initdata =
- KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
+static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
static struct uart_driver sci_uart_driver = {
.owner = THIS_MODULE,
static const struct of_device_id of_sci_match[] = {
{
.compatible = "renesas,scif",
- .data = (void *)&(const struct sci_port_info) {
+ .data = &(const struct sci_port_info) {
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
},
}, {
.compatible = "renesas,scifa",
- .data = (void *)&(const struct sci_port_info) {
+ .data = &(const struct sci_port_info) {
.type = PORT_SCIFA,
.regtype = SCIx_SCIFA_REGTYPE,
},
}, {
.compatible = "renesas,scifb",
- .data = (void *)&(const struct sci_port_info) {
+ .data = &(const struct sci_port_info) {
.type = PORT_SCIFB,
.regtype = SCIx_SCIFB_REGTYPE,
},
}, {
.compatible = "renesas,hscif",
- .data = (void *)&(const struct sci_port_info) {
+ .data = &(const struct sci_port_info) {
.type = PORT_HSCIF,
.regtype = SCIx_HSCIF_REGTYPE,
},
/* Sanity check */
if (unlikely(index >= SCI_NPORTS)) {
- dev_notice(&dev->dev, "Attempting to register port "
- "%d when only %d are available.\n",
+ dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
index+1, SCI_NPORTS);
- dev_notice(&dev->dev, "Consider bumping "
- "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
+ dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
return -EINVAL;
}
ret = cpufreq_register_notifier(&sp->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
if (unlikely(ret < 0)) {
+ uart_remove_one_port(&sci_uart_driver, &sp->port);
sci_cleanup_single(sp);
return ret;
}
{
int ret;
- printk(banner);
+ pr_info("%s\n", banner);
ret = uart_register_driver(&sci_uart_driver);
if (likely(ret == 0)) {
projects / platform / adaptation / renesas_rcar / renesas_kernel.git / blobdiff