Tundra tsi108 header file.

[platform/kernel/u-boot.git] / drivers / tsec.h

diff --git a/drivers/tsec.h b/drivers/tsec.h
index 15961d7..4aa331c 100644 (file)
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -27,7 +27,7 @@
 #define TSEC_SIZE      0x01000
 
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
     #define TSEC_BASE_ADDR     (CFG_IMMR + CFG_TSEC1_OFFSET)
 #elif defined(CONFIG_MPC83XX)
     #define TSEC_BASE_ADDR     (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
@@ -40,6 +40,8 @@
 #define TSEC_TIMEOUT 1000
 #define TOUT_LOOP      1000000
 
+#define PHY_AUTONEGOTIATE_TIMEOUT      5000 /* in ms */
+
 /* MAC register bits */
 #define MACCFG1_SOFT_RESET     0x80000000
 #define MACCFG1_RESET_RX_MC    0x00080000
@@ -77,6 +79,7 @@
 #define MIIM_CONTROL            0x00
 #define MIIM_CONTROL_RESET     0x00009140
 #define MIIM_CONTROL_INIT       0x00001140
+#define MIIM_CONTROL_RESTART    0x00001340
 #define MIIM_ANEN               0x00001000
 
 #define MIIM_CR                 0x00
@@ -86,6 +89,8 @@
 #define MIIM_STATUS            0x1
 #define MIIM_STATUS_AN_DONE    0x00000020
 #define MIIM_STATUS_LINK       0x0004
+#define PHY_BMSR_AUTN_ABLE     0x0008
+#define PHY_BMSR_AUTN_COMP     0x0020
 
 #define MIIM_PHYIR1            0x2
 #define MIIM_PHYIR2            0x3
@@ -119,7 +124,7 @@
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON          0x17
 #define MIIM_CIS8204_EPHYCON_INIT      0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII     0x1000
+#define MIIM_CIS8204_EPHYCON_RGMII     0x1100
 
 /* Cicada 8204 Serial LED Control Register */
 #define MIIM_CIS8204_SLED_CON          0x1b
@@ -128,6 +133,24 @@
 #define MIIM_GBIT_CON          0x09
 #define MIIM_GBIT_CON_ADVERT   0x0e00
 
+/* Entry for Vitesse VSC8244 regs starts here */
+/* Vitesse VSC8244 Auxiliary Control/Status Register */
+#define MIIM_VSC8244_AUX_CONSTAT        0x1c
+#define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
+#define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
+#define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
+#define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
+#define MIIM_VSC8244_AUXCONSTAT_100     0x0008
+#define MIIM_CONTROL_INIT_LOOPBACK      0x4000
+
+/* Vitesse VSC8244 Extended PHY Control Register 1 */
+#define MIIM_VSC8244_EPHY_CON           0x17
+#define MIIM_VSC8244_EPHYCON_INIT       0x0006
+
+/* Vitesse VSC8244 Serial LED Control Register */
+#define MIIM_VSC8244_LED_CON            0x1b
+#define MIIM_VSC8244_LEDCON_INIT        0xF011
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000
@@ -137,6 +160,23 @@
 #define MIIM_88E1011_PHYSTAT_SPDDONE   0x0800
 #define MIIM_88E1011_PHYSTAT_LINK      0x0400
 
+#define MIIM_88E1011_PHY_SCR           0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO    0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL   24
+#define MIIM_88E1111_PHY_LED_DIRECT    0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE   0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY   0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY   0x0002
+
+#define MIIM_88E1145_PHY_PAGE   29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
 /* DM9161 Control register values */
 #define MIIM_DM9161_CR_STOP    0x0400
 #define MIIM_DM9161_CR_RSTAN   0x1200
@@ -156,12 +196,22 @@
 #define MIIM_DM9161_10BTCSR_INIT       0x7800
 
 /* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2        17  /* Status Register 2  */
-#define MIIM_LXT971_SR2_SPEED_MASK     0xf000
-#define MIIM_LXT971_SR2_10HDX  0x1000  /* 10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX  0x2000  /* 10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX 0x4000  /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX 0x8000  /* 100 Mbit full duplex selected */
+#define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
+#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
+#define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
+
+/* DP83865 Control register values */
+#define MIIM_DP83865_CR_INIT   0x9200
+
+/* DP83865 Link and Auto-Neg Status Register */
+#define MIIM_DP83865_LANR      0x11
+#define MIIM_DP83865_SPD_MASK  0x0018
+#define MIIM_DP83865_SPD_1000  0x0010
+#define MIIM_DP83865_SPD_100   0x0008
+#define MIIM_DP83865_DPX_FULL  0x0002
 
 #define MIIM_READ_COMMAND       0x00000001