common: Drop asm/global_data.h from common header

[platform/kernel/u-boot.git] / drivers / timer / tsc_timer.c

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 6473de2..7d19a99 100644 (file)
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -7,20 +7,75 @@
  */
 
 #include <common.h>
+#include <bootstage.h>
 #include <dm.h>
+#include <log.h>
 #include <malloc.h>
+#include <time.h>
 #include <timer.h>
 #include <asm/cpu.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/i8254.h>
 #include <asm/ibmpc.h>
 #include <asm/msr.h>
 #include <asm/u-boot-x86.h>
+#include <linux/delay.h>
 
 #define MAX_NUM_FREQS  9
 
+#define INTEL_FAM6_SKYLAKE_MOBILE      0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT       0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP     0x5E
+#define INTEL_FAM6_ATOM_GOLDMONT_X     0x5F /* Denverton */
+#define INTEL_FAM6_KABYLAKE_MOBILE     0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP    0x9E
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+       struct cpuid_result tsc_info;
+       unsigned int crystal_freq;
+
+       if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+               return 0;
+
+       if (cpuid_eax(0) < 0x15)
+               return 0;
+
+       tsc_info = cpuid(0x15);
+
+       if (tsc_info.ebx == 0 || tsc_info.eax == 0)
+               return 0;
+
+       crystal_freq = tsc_info.ecx / 1000;
+       if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
+               switch (gd->arch.x86_model) {
+               case INTEL_FAM6_SKYLAKE_MOBILE:
+               case INTEL_FAM6_SKYLAKE_DESKTOP:
+               case INTEL_FAM6_KABYLAKE_MOBILE:
+               case INTEL_FAM6_KABYLAKE_DESKTOP:
+                       crystal_freq = 24000;   /* 24.0 MHz */
+                       break;
+               case INTEL_FAM6_ATOM_GOLDMONT_X:
+                       crystal_freq = 25000;   /* 25.0 MHz */
+                       break;
+               case INTEL_FAM6_ATOM_GOLDMONT:
+                       crystal_freq = 19200;   /* 19.2 MHz */
+                       break;
+               default:
+                       return 0;
+               }
+       }
+
+       return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
 static unsigned long cpu_mhz_from_cpuid(void)
 {
        if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -318,7 +373,7 @@ void __udelay(unsigned long usec)
        u64 now = get_ticks();
        u64 stop;
 
-       stop = now + usec * get_tbclk_mhz();
+       stop = now + (u64)usec * get_tbclk_mhz();
 
        while ((int64_t)(stop - get_ticks()) > 0)
 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
@@ -332,24 +387,31 @@ void __udelay(unsigned long usec)
 #endif
 }
 
-static int tsc_timer_get_count(struct udevice *dev, u64 *count)
+static u64 tsc_timer_get_count(struct udevice *dev)
 {
        u64 now_tick = rdtsc();
 
-       *count = now_tick - gd->arch.tsc_base;
-
-       return 0;
+       return now_tick - gd->arch.tsc_base;
 }
 
-static void tsc_timer_ensure_setup(bool stop)
+static void tsc_timer_ensure_setup(bool early)
 {
-       if (gd->arch.tsc_base)
+       if (gd->arch.tsc_inited)
                return;
-       gd->arch.tsc_base = rdtsc();
+       if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
+               gd->arch.tsc_base = rdtsc();
 
        if (!gd->arch.clock_rate) {
                unsigned long fast_calibrate;
 
+               fast_calibrate = native_calibrate_tsc();
+               if (fast_calibrate)
+                       goto done;
+
+               /* Reduce code size by dropping other methods */
+               if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
+                       panic("no timer");
+
                fast_calibrate = cpu_mhz_from_cpuid();
                if (fast_calibrate)
                        goto done;
@@ -362,14 +424,15 @@ static void tsc_timer_ensure_setup(bool stop)
                if (fast_calibrate)
                        goto done;
 
-               if (stop)
-                       panic("TSC frequency is ZERO");
+               if (early)
+                       fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
                else
                        return;
 
 done:
                gd->arch.clock_rate = fast_calibrate * 1000000;
        }
+       gd->arch.tsc_inited = true;
 }
 
 static int tsc_timer_probe(struct udevice *dev)
@@ -406,6 +469,8 @@ unsigned long notrace timer_early_get_rate(void)
 
 u64 notrace timer_early_get_count(void)
 {
+       tsc_timer_ensure_setup(true);
+
        return rdtsc() - gd->arch.tsc_base;
 }
 
@@ -413,16 +478,17 @@ static const struct timer_ops tsc_timer_ops = {
        .get_count = tsc_timer_get_count,
 };
 
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 static const struct udevice_id tsc_timer_ids[] = {
        { .compatible = "x86,tsc-timer", },
        { }
 };
+#endif
 
-U_BOOT_DRIVER(tsc_timer) = {
-       .name   = "tsc_timer",
+U_BOOT_DRIVER(x86_tsc_timer) = {
+       .name   = "x86_tsc_timer",
        .id     = UCLASS_TIMER,
-       .of_match = tsc_timer_ids,
+       .of_match = of_match_ptr(tsc_timer_ids),
        .probe = tsc_timer_probe,
        .ops    = &tsc_timer_ops,
-       .flags = DM_FLAG_PRE_RELOC,
 };