/* io defines */
#if !defined(BIG_ENDIAN_HOST)
#define readl(addr) \
- (LONGSWAP((*(volatile unsigned int *)(addr))))
+ (LONGSWAP((*(volatile unsigned int *)(addr))))
#define writel(b,addr) \
- ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
+ ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
#else
#if 0 /* !defined(PPC603) */
#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
#endif
-
-
/******************************************************************************/
/* Constants. */
/******************************************************************************/
#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
- MAX_FRAGMENT_COUNT)
+ MAX_FRAGMENT_COUNT)
/* MAGIC number. */
/* #define T3_MAGIC_NUM 'KevT' */
#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000
#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \
- sizeof(T3_SND_BD) / 4)
+ sizeof(T3_SND_BD) / 4)
#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \
- sizeof(T3_RCV_BD) / 4)
+ sizeof(T3_RCV_BD) / 4)
#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
- sizeof(T3_EXT_RCV_BD) / 4)
+ sizeof(T3_EXT_RCV_BD) / 4)
/* MBUF pool. */
} T3_FWIMG_INFO, *PT3_FWIMG_INFO;
-
/******************************************************************************/
/* Tigon3 PCI Registers. */
/******************************************************************************/
#define PHY_AN_EXPANSION_REG 0x06
-
/******************************************************************************/
/* BCM5400 and BCM5401 phy info. */
/******************************************************************************/
#define PHY_ID_MODEL_MASK 0x000003f0
#define PHY_ID_REV_MASK 0x0000000f
#define PHY_ID_MASK (PHY_ID_OUI_MASK | \
- PHY_ID_MODEL_MASK)
+ PHY_ID_MODEL_MASK)
#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
-
+ (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
+ (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
+ (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
+ (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
+ (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
+ (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
/* 1000Base-T control register. */
#define BCM540X_INT_MASK_REG 0x1b
-
/******************************************************************************/
/* Register definitions. */
/******************************************************************************/
}T3_DMA_DESC, *PT3_DMA_DESC;
-
/******************************************************************************/
/* Ring control block. */
/******************************************************************************/
T3_64BIT_REGISTER HostRingAddr;
union {
- struct {
+ struct {
#ifdef BIG_ENDIAN_HOST
- T3_16BIT_REGISTER MaxLen;
- T3_16BIT_REGISTER Flags;
+ T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER Flags;
#else /* BIG_ENDIAN_HOST */
- T3_16BIT_REGISTER Flags;
- T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER Flags;
+ T3_16BIT_REGISTER MaxLen;
#endif
- } s;
+ } s;
- T3_32BIT_REGISTER MaxLen_Flags;
+ T3_32BIT_REGISTER MaxLen_Flags;
} u;
T3_32BIT_REGISTER NicRingAddr;
#define T3_RCB_FLAG_RING_DISABLED BIT_1
-
/******************************************************************************/
/* Status block. */
/******************************************************************************/
volatile LM_UINT16 RcvMiniConIdx;
struct {
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
} Idx[16];
#else /* BIG_ENDIAN_HOST */
volatile LM_UINT16 RcvJumboConIdx;
volatile LM_UINT16 Reserved2;
struct {
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
} Idx[16];
#endif
} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
-
/******************************************************************************/
/* Receive buffer descriptors. */
/******************************************************************************/
#define RCV_BD_FLAG_TCP_PACKET 0x4000
-
/******************************************************************************/
/* Send buffer descriptor. */
/******************************************************************************/
T3_64BIT_HOST_ADDR HostAddr;
union {
- struct {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len;
- LM_UINT16 Flags;
+ LM_UINT16 Len;
+ LM_UINT16 Flags;
#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Flags;
- LM_UINT16 Len;
+ LM_UINT16 Flags;
+ LM_UINT16 Len;
#endif
- } s1;
+ } s1;
- LM_UINT32 Len_Flags;
+ LM_UINT32 Len_Flags;
} u1;
union {
- struct {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Reserved;
- LM_UINT16 VlanTag;
+ LM_UINT16 Reserved;
+ LM_UINT16 VlanTag;
#else /* BIG_ENDIAN_HOST */
- LM_UINT16 VlanTag;
- LM_UINT16 Reserved;
+ LM_UINT16 VlanTag;
+ LM_UINT16 Reserved;
#endif
- } s2;
+ } s2;
- LM_UINT32 VlanTag;
+ LM_UINT32 VlanTag;
} u2;
} T3_SND_BD, *PT3_SND_BD;
#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
-
/******************************************************************************/
/* Statistics block. */
/******************************************************************************/
} T3_STATS_BLOCK, *PT3_STATS_BLOCK;
-
/******************************************************************************/
/* PCI configuration registers. */
/******************************************************************************/
/* MAC addresses. */
struct {
- T3_32BIT_REGISTER High; /* Upper 2 bytes. */
- T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
+ T3_32BIT_REGISTER High; /* Upper 2 bytes. */
+ T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
} MacAddr[4];
/* ACPI Mbuf pointer. */
/* Receive placement rules registers. */
struct {
- T3_32BIT_REGISTER Rule;
- T3_32BIT_REGISTER Value;
+ T3_32BIT_REGISTER Rule;
+ T3_32BIT_REGISTER Value;
} RcvRules[16];
#define RCV_DISABLE_RULE_MASK 0x7fffffff
} T3_MAC_CONTROL, *PT3_MAC_CONTROL;
-
/******************************************************************************/
/* Send data initiator control registers. */
/******************************************************************************/
} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
-
/******************************************************************************/
/* Send data completion control registers. */
/******************************************************************************/
} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
-
/******************************************************************************/
/* Send BD Ring Selector Control Registers. */
/******************************************************************************/
} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
-
/******************************************************************************/
/* Send BD initiator control registers. */
/******************************************************************************/
} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
-
/******************************************************************************/
/* Send BD Completion Control. */
/******************************************************************************/
} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list placement control registers. */
/******************************************************************************/
LM_UINT8 Unused1[224];
struct {
- T3_32BIT_REGISTER Head;
- T3_32BIT_REGISTER Tail;
- T3_32BIT_REGISTER Count;
+ T3_32BIT_REGISTER Head;
+ T3_32BIT_REGISTER Tail;
+ T3_32BIT_REGISTER Count;
- /* Unused space. */
- LM_UINT8 Unused[4];
+ /* Unused space. */
+ LM_UINT8 Unused[4];
} RcvSelectorList[16];
/* Local statistics counter. */
} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
-
/******************************************************************************/
/* Receive Data and Receive BD Initiator Control. */
/******************************************************************************/
} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
-
/******************************************************************************/
/* Receive Data Completion Control Registes. */
/******************************************************************************/
} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
-
/******************************************************************************/
/* Receive BD Initiator Control. */
/******************************************************************************/
} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
-
/******************************************************************************/
/* Receive BD Completion Control Registers. */
/******************************************************************************/
} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list selector control register. */
/******************************************************************************/
} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
-
/******************************************************************************/
/* Mbuf cluster free registers. */
/******************************************************************************/
} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
-
/******************************************************************************/
/* Host coalescing control registers. */
/******************************************************************************/
} T3_HOST_COALESCING, *PT3_HOST_COALESCING;
-
/******************************************************************************/
/* Memory arbiter registers. */
/******************************************************************************/
} T3_MEM_ARBITER, *PT3_MEM_ARBITER;
-
/******************************************************************************/
/* Buffer manager control register. */
/******************************************************************************/
} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
-
/******************************************************************************/
/* Read DMA control registers. */
/******************************************************************************/
} T3_DMA_WRITE, *PT3_DMA_WRITE;
-
/******************************************************************************/
/* Mailbox registers. */
/******************************************************************************/
} T3_FTQ, *PT3_FTQ;
-
/******************************************************************************/
/* Message signaled interrupt registers. */
/******************************************************************************/
} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
-
/******************************************************************************/
/* DMA Completion registes. */
/******************************************************************************/
} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
-
/******************************************************************************/
/* GRC registers. */
/******************************************************************************/
} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
-
/******************************************************************************/
/* Memory layout. */
/******************************************************************************/
/* Address register. This register is located */
/* in the PCI configuration space. */
union { /* 0x8000 */
- T3_FIRST_32K_SRAM First32k;
+ T3_FIRST_32K_SRAM First32k;
- /* Use the memory window base address register to determine the */
- /* MBUF segment. */
- LM_UINT32 Mbuf[32768/4];
- LM_UINT32 MemBlock32K[32768/4];
+ /* Use the memory window base address register to determine the */
+ /* MBUF segment. */
+ LM_UINT32 Mbuf[32768/4];
+ LM_UINT32 MemBlock32K[32768/4];
} uIntMem;
} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
-
/******************************************************************************/
/* Tx counters. */
/******************************************************************************/
} LM_TX_COUNTERS, *PLM_TX_COUNTERS;
-
/******************************************************************************/
/* Rx counters. */
/******************************************************************************/
} LM_RX_COUNTERS, *PLM_RX_COUNTERS;
-
/******************************************************************************/
/* Receive producer rings. */
/******************************************************************************/
} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
-
/******************************************************************************/
/* Packet descriptor. */
/******************************************************************************/
LM_UINT16 VlanTag;
union {
- /* Send info. */
- struct {
- /* Set up by UM. */
- LM_UINT32 FragCount;
+ /* Send info. */
+ struct {
+ /* Set up by UM. */
+ LM_UINT32 FragCount;
- } Tx;
+ } Tx;
- /* Receive info. */
- struct {
- /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
- T3_RCV_PROD_RING RcvProdRing;
+ /* Receive info. */
+ struct {
+ /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
+ T3_RCV_PROD_RING RcvProdRing;
- /* Receive buffer size */
- LM_UINT32 RxBufferSize;
+ /* Receive buffer size */
+ LM_UINT32 RxBufferSize;
- /* Checksum information. */
- LM_UINT16 IpChecksum;
- LM_UINT16 TcpUdpChecksum;
+ /* Checksum information. */
+ LM_UINT16 IpChecksum;
+ LM_UINT16 TcpUdpChecksum;
- } Rx;
+ } Rx;
} u;
} LM_PACKET;
-
/******************************************************************************/
/* Tigon3 device block. */
/******************************************************************************/
#define T3_QID_SW_TYPE2 17
LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu,
- LM_UINT32 StartCpu);
+ PT3_FWIMG_INFO pFwImg,
+ LM_UINT32 LoadCpu,
+ LM_UINT32 StartCpu);
/******************************************************************************/
/* NIC register read/write macros. */
#define MB_REG_WR(pDevice, OffsetName, Value32) \
((pDevice)->UndiFix) ? \
- LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \
- Value32) : \
- (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
+ LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \
+ Value32) : \
+ (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
#define MB_REG_RD(pDevice, OffsetName) \
(((pDevice)->UndiFix) ? \
- LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \
- __raw_readl(&((pDevice)->pMemView->OffsetName)))
+ LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \
+ __raw_readl(&((pDevice)->pMemView->OffsetName)))
#define REG_RD(pDevice, OffsetName) \
(((pDevice)->UndiFix) ? \
- LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \
- __raw_readl(&((pDevice)->pMemView->OffsetName)))
+ LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \
+ __raw_readl(&((pDevice)->pMemView->OffsetName)))
#if PCIX_TARGET_WORKAROUND
LM_MemWrInd(pDevice, Offset, Value32)
#endif /* TIGON3_H */
-
projects / kernel / u-boot.git / blobdiff