+// SPDX-License-Identifier: GPL-2.0-only
/*
* Phy provider for USB 3.1 controller on HiSilicon Kirin970 platform
*
- * Copyright (C) 2017-2018 Hilisicon Electronics Co., Ltd.
+ * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd.
* http://www.huawei.com
*
* Authors: Yu Chen <chenyu56@huawei.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/platform_device.h>
#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
-#include <linux/clk.h>
#define SCTRL_SCDEEPSLEEPED (0x0)
#define USB_CLK_SELECTED BIT(20)
#define TCPC_VALID BIT(4)
#define TCPC_LOW_POWER_EN BIT(3)
#define TCPC_MUX_CONTROL_MASK (3 << 0)
-#define TCPC_MUX_CONTROL_USB31 (1 << 0)
+#define TCPC_MUX_CONTROL_USB31 BIT(0)
#define SYSMODE_CFG_TYPEC_DISABLE BIT(3)
/* Clock up */
ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK);
+ CFG54_USB31PHY_CR_CLK, CFG54_USB31PHY_CR_CLK);
if (ret)
return ret;
/* Clock down */
ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_CLK, 0);
+ CFG54_USB31PHY_CR_CLK, 0);
return ret;
}
static int hi3670_phy_cr_set_sel(struct regmap *usb31misc)
{
return regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL);
+ CFG54_USB31PHY_CR_SEL, CFG54_USB31PHY_CR_SEL);
}
static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction)
if (direction)
ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_WR_EN, CFG54_USB31PHY_CR_WR_EN);
+ CFG54_USB31PHY_CR_WR_EN,
+ CFG54_USB31PHY_CR_WR_EN);
else
ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_RD_EN, CFG54_USB31PHY_CR_RD_EN);
+ CFG54_USB31PHY_CR_RD_EN,
+ CFG54_USB31PHY_CR_RD_EN);
if (ret)
return ret;
return ret;
ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
- CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0);
+ CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0);
return ret;
}
return ret;
reg &= ~(CFG54_USB31PHY_CR_ADDR_MASK << CFG54_USB31PHY_CR_ADDR_SHIFT);
- reg |= ((addr & CFG54_USB31PHY_CR_ADDR_MASK) <<
- CFG54_USB31PHY_CR_ADDR_SHIFT);
+ reg |= ((addr & CFG54_USB31PHY_CR_ADDR_MASK) << CFG54_USB31PHY_CR_ADDR_SHIFT);
ret = regmap_write(usb31misc, USB_MISC_CFG54, reg);
return ret;
return ret;
ret = regmap_write(usb31misc, USB_MISC_CFG58,
- val & CFG58_USB31PHY_CR_DATA_MASK);
+ val & CFG58_USB31PHY_CR_DATA_MASK);
if (ret)
return ret;
int retry = 3;
ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4,
- priv->eye_diagram_param);
+ priv->eye_diagram_param);
if (ret) {
dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n");
return ret;
while (retry-- > 0) {
ret = hi3670_phy_cr_read(priv->usb31misc,
- TX_VBOOST_LVL_REG, ®);
+ TX_VBOOST_LVL_REG, ®);
if (!ret)
break;
- else if (ret != -ETIMEDOUT) {
+
+ if (ret != -ETIMEDOUT) {
dev_err(priv->dev, "read TX_VBOOST_LVL_REG failed\n");
return ret;
}
if (ret)
return ret;
- reg |= (TX_VBOOST_LVL_ENABLE |
- (priv->tx_vboost_lvl << TX_VBOOST_LVL_START));
+ reg |= (TX_VBOOST_LVL_ENABLE | (priv->tx_vboost_lvl << TX_VBOOST_LVL_START));
ret = hi3670_phy_cr_write(priv->usb31misc, TX_VBOOST_LVL_REG, reg);
if (ret)
dev_err(priv->dev, "write TX_VBOOST_LVL_REG failed\n");
if (hi3670_is_abbclk_seleted(priv)) {
/* usb refclk iso disable */
ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS,
- USB_REFCLK_ISO_EN);
+ USB_REFCLK_ISO_EN);
if (ret)
goto out;
/* enable usb_tcxo_en */
ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3,
- USB_TCXO_EN |
- (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START));
+ USB_TCXO_EN |
+ (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START));
/* select usbphy clk from abb */
mask = SC_CLK_USB3PHY_3MUX1_SEL;
ret = regmap_update_bits(priv->pctrl,
- PCTRL_PERI_CTRL24, mask, 0);
+ PCTRL_PERI_CTRL24, mask, 0);
if (ret)
goto out;
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0,
- CFGA0_USB2PHY_REFCLK_SELECT, 0);
+ CFGA0_USB2PHY_REFCLK_SELECT, 0);
if (ret)
goto out;
ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val);
if (ret)
goto out;
- } else {
- ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54,
- CFG54_USB3PHY_REF_USE_PAD,
- CFG54_USB3PHY_REF_USE_PAD);
- if (ret)
- goto out;
- ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0,
- CFGA0_USB2PHY_REFCLK_SELECT,
- CFGA0_USB2PHY_REFCLK_SELECT);
- if (ret)
- goto out;
+ return 0;
+ }
- ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val);
- if (ret)
- goto out;
- val &= ~CTRL7_USB2_REFCLKSEL_MASK;
- val |= CTRL7_USB2_REFCLKSEL_PAD;
- ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val);
- if (ret)
- goto out;
+ ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54,
+ CFG54_USB3PHY_REF_USE_PAD,
+ CFG54_USB3PHY_REF_USE_PAD);
+ if (ret)
+ goto out;
- ret = regmap_write(priv->peri_crg,
- PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF);
- if (ret)
- goto out;
- }
+ ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0,
+ CFGA0_USB2PHY_REFCLK_SELECT,
+ CFGA0_USB2PHY_REFCLK_SELECT);
+ if (ret)
+ goto out;
+
+ ret = regmap_read(priv->usb31misc, USB3OTG_CTRL7, &val);
+ if (ret)
+ goto out;
+ val &= ~CTRL7_USB2_REFCLKSEL_MASK;
+ val |= CTRL7_USB2_REFCLKSEL_PAD;
+ ret = regmap_write(priv->usb31misc, USB3OTG_CTRL7, val);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(priv->peri_crg,
+ PERI_CRG_PEREN6, GT_CLK_USB2PHY_REF);
+ if (ret)
+ goto out;
return 0;
out:
goto out;
ret = regmap_write(priv->usb31misc, TCA_INTR_EN,
- INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN);
+ INTR_EN_XA_TIMEOUT_EVT_EN | INTR_EN_XA_ACK_EVT_EN);
if (ret)
goto out;
goto out;
ret = regmap_update_bits(priv->usb31misc, TCA_GCFG,
- GCFG_ROLE_HSTDEV | GCFG_OP_MODE,
- GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE);
+ GCFG_ROLE_HSTDEV | GCFG_OP_MODE,
+ GCFG_ROLE_HSTDEV | GCFG_OP_MODE_CTRL_SYNC_MODE);
if (ret)
goto out;
ret = regmap_update_bits(priv->usb31misc, TCA_SYSMODE_CFG,
- SYSMODE_CFG_TYPEC_DISABLE, 0);
+ SYSMODE_CFG_TYPEC_DISABLE, 0);
if (ret)
goto out;
goto out;
ret = regmap_write(priv->usb31misc, TCA_VBUS_CTRL,
- VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD);
+ VBUS_CTRL_POWERPRESENT_OVERRD | VBUS_CTRL_VBUSVALID_OVERRD);
if (ret)
goto out;
/* assert controller */
val = CFGA0_VAUX_RESET | CFGA0_USB31C_RESET |
- CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR;
+ CFGA0_USB3PHY_RESET | CFGA0_USB2PHY_POR;
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFGA0, val, 0);
if (ret)
goto out;
/* Exit from IDDQ mode */
ret = regmap_update_bits(priv->usb31misc, USB3OTG_CTRL5,
- CTRL5_USB2_SIDDQ, 0);
+ CTRL5_USB2_SIDDQ, 0);
if (ret)
goto out;
/* Release USB31 PHY out of TestPowerDown mode */
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG50,
- CFG50_USB3_PHY_TEST_POWERDOWN, 0);
+ CFG50_USB3_PHY_TEST_POWERDOWN, 0);
if (ret)
goto out;
if (ret)
goto out;
- udelay(100);
+ usleep_range(100, 120);
/* Tell the PHY power is stable */
val = CFG54_USB3_PHY0_ANA_PWR_EN | CFG54_PHY0_PCS_PWR_STABLE |
- CFG54_PHY0_PMA_PWR_STABLE;
+ CFG54_PHY0_PMA_PWR_STABLE;
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG54,
- val, val);
+ val, val);
if (ret)
goto out;
/* Enable SSC */
ret = regmap_update_bits(priv->usb31misc, USB_MISC_CFG5C,
- CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN,
- CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN);
+ CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN,
+ CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN);
if (ret)
goto out;
if (ret)
goto out;
- udelay(100);
+ usleep_range(100, 120);
/* Set fake vbus valid signal */
val = CTRL0_USB3_VBUSVLD | CTRL0_USB3_VBUSVLD_SEL;
if (ret)
goto out;
- udelay(100);
+ usleep_range(100, 120);
ret = hi3670_phy_set_params(priv);
if (ret)
if (hi3670_is_abbclk_seleted(priv)) {
/* disable usb_tcxo_en */
ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3,
- USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START);
+ USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START);
} else {
ret = regmap_write(priv->peri_crg, PERI_CRG_PERDIS6,
- GT_CLK_USB2PHY_REF);
+ GT_CLK_USB2PHY_REF);
if (ret)
goto out;
}
priv->dev = dev;
priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node,
- "hisilicon,pericrg-syscon");
+ "hisilicon,pericrg-syscon");
if (IS_ERR(priv->peri_crg)) {
dev_err(dev, "no hisilicon,pericrg-syscon\n");
return PTR_ERR(priv->peri_crg);
}
priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
- "hisilicon,pctrl-syscon");
+ "hisilicon,pctrl-syscon");
if (IS_ERR(priv->pctrl)) {
dev_err(dev, "no hisilicon,pctrl-syscon\n");
return PTR_ERR(priv->pctrl);
}
priv->sctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
- "hisilicon,sctrl-syscon");
+ "hisilicon,sctrl-syscon");
if (IS_ERR(priv->sctrl)) {
dev_err(dev, "no hisilicon,sctrl-syscon\n");
return PTR_ERR(priv->sctrl);
}
priv->usb31misc = syscon_regmap_lookup_by_phandle(dev->of_node,
- "hisilicon,usb31-misc-syscon");
+ "hisilicon,usb31-misc-syscon");
if (IS_ERR(priv->usb31misc)) {
dev_err(dev, "no hisilicon,usb31-misc-syscon\n");
return PTR_ERR(priv->usb31misc);
}
if (of_property_read_u32(dev->of_node, "eye-diagram-param",
- &(priv->eye_diagram_param)))
+ &priv->eye_diagram_param))
priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_PARAM;
if (of_property_read_u32(dev->of_node, "usb3-phy-tx-vboost-lvl",
- &(priv->tx_vboost_lvl)))
+ &priv->tx_vboost_lvl))
priv->eye_diagram_param = KIRIN970_USB_DEFAULT_PHY_VBOOST;
phy = devm_phy_create(dev, NULL, &hi3670_phy_ops);
}
static const struct of_device_id hi3670_phy_of_match[] = {
- {.compatible = "hisilicon,hi3670-usb-phy",},
+ { .compatible = "hisilicon,hi3670-usb-phy" },
{ },
};
MODULE_DEVICE_TABLE(of, hi3670_phy_of_match);
projects / platform / kernel / linux-starfive.git / blobdiff