#include <spi.h>
#include <time.h>
#include <clk.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
/* zynq spi platform data */
-struct zynq_spi_platdata {
+struct zynq_spi_plat {
struct zynq_spi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
u32 freq; /* required frequency */
};
-static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
+static int zynq_spi_of_to_plat(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_spi_probe(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
u32 tx_len = len, rx_len = len, tx_tvl;
const u8 *tx_buf = dout;
u32 ts, status;
debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
- bus->seq, slave_plat->cs, bitlen, len, flags);
+ dev_seq(bus), slave_plat->cs, bitlen, len, flags);
if (bitlen % 8) {
debug("spi_xfer: Non byte aligned SPI transfer\n");
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_spi_platdata *plat = bus->platdata;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
uint32_t confr;
.id = UCLASS_SPI,
.of_match = zynq_spi_ids,
.ops = &zynq_spi_ops,
- .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
+ .of_to_plat = zynq_spi_of_to_plat,
+ .plat_auto = sizeof(struct zynq_spi_plat),
+ .priv_auto = sizeof(struct zynq_spi_priv),
.probe = zynq_spi_probe,
};