#include <spi.h>
#include <time.h>
#include <clk.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
static int zynq_spi_of_to_plat(struct udevice *bus)
{
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
uint32_t confr;