+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013 Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
*
* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
+#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
-#endif
+#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq qspi register set */
struct zynq_qspi_regs {
{
struct zynq_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
do {
status = readl(®s->isr);
} while ((status == 0) &&
- (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
+ (get_timer(timeout) < ZYNQ_QSPI_WAIT));
if (status == 0) {
printf("zynq_qspi_irq_poll: Timeout!\n");
break;
}
- return 0;
+ return status;
}
static int zynq_qspi_claim_bus(struct udevice *dev)