*
* Copyright (c) 2010-2013 NVIDIA Corporation
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
/* COMMAND1 */
#define SPI_CMD1_GO BIT(31)
#define SPI_CMD1_M_S BIT(30)
-#define SPI_CMD1_MODE_MASK 0x3
+#define SPI_CMD1_MODE_MASK GENMASK(1, 0)
#define SPI_CMD1_MODE_SHIFT 28
-#define SPI_CMD1_CS_SEL_MASK 0x3
+#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
#define SPI_CMD1_CS_SEL_SHIFT 26
#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
#define SPI_CMD1_CS_SW_HW BIT(21)
#define SPI_CMD1_CS_SW_VAL BIT(20)
-#define SPI_CMD1_IDLE_SDA_MASK 0x3
+#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
#define SPI_CMD1_IDLE_SDA_SHIFT 18
#define SPI_CMD1_BIDIR BIT(17)
#define SPI_CMD1_LSBI_FE BIT(16)
#define SPI_CMD1_RX_EN BIT(12)
#define SPI_CMD1_TX_EN BIT(11)
#define SPI_CMD1_PACKED BIT(5)
-#define SPI_CMD1_BIT_LEN_MASK 0x1F
+#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
#define SPI_CMD1_BIT_LEN_SHIFT 0
/* COMMAND2 */
#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
-#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
-#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
/* TRANSFER STATUS */
#define SPI_XFER_STS_RDY BIT(30)
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
- plat->base = dev_get_addr(bus);
+ plat->base = devfdt_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
bus->name, priv->freq, rate);
}
}
+ udelay(plat->deactivate_delay_us);
/* Clear stale status here */
setbits_le32(®s->fifo_status,