{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
- plat->base = dev_get_addr(bus);
+ plat->base = devfdt_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
bus->name, priv->freq, rate);
}
}
+ udelay(plat->deactivate_delay_us);
/* Clear stale status here */
setbits_le32(®s->fifo_status,