spi: aspeed: Fix window offset of CE1

[platform/kernel/linux-rpi.git] / drivers / spi / spi-aspeed-smc.c

diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 3e891bf..b905713 100644 (file)
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -398,7 +398,7 @@ static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
                windows[cs].cs = cs;
                windows[cs].size = data->segment_end(aspi, reg_val) -
                        data->segment_start(aspi, reg_val);
-               windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
+               windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy;
                dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
                         windows[cs].offset, windows[cs].size);
        }
@@ -736,10 +736,8 @@ static int aspeed_spi_probe(struct platform_device *pdev)
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        aspi->regs = devm_ioremap_resource(dev, res);
-       if (IS_ERR(aspi->regs)) {
-               dev_err(dev, "missing AHB register window\n");
+       if (IS_ERR(aspi->regs))
                return PTR_ERR(aspi->regs);
-       }
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
        aspi->ahb_base = devm_ioremap_resource(dev, res);
@@ -1165,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = {
 static const struct aspeed_spi_data ast2600_fmc_data = {
        .max_cs        = 3,
        .hastype       = false,
-       .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
+       .mode_bits     = SPI_RX_QUAD | SPI_TX_QUAD,
        .we0           = 16,
        .ctl0          = CE0_CTRL_REG,
        .timing        = CE0_TIMING_COMPENSATION_REG,
@@ -1180,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
 static const struct aspeed_spi_data ast2600_spi_data = {
        .max_cs        = 2,
        .hastype       = false,
-       .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
+       .mode_bits     = SPI_RX_QUAD | SPI_TX_QUAD,
        .we0           = 16,
        .ctl0          = CE0_CTRL_REG,
        .timing        = CE0_TIMING_COMPENSATION_REG,