#include <malloc.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <omap3_spi.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
-#define OMAP3_MCSPI1_BASE 0x48030100
-#define OMAP3_MCSPI2_BASE 0x481A0100
-#else
-#define OMAP3_MCSPI1_BASE 0x48098000
-#define OMAP3_MCSPI2_BASE 0x4809A000
-#define OMAP3_MCSPI3_BASE 0x480B8000
-#define OMAP3_MCSPI4_BASE 0x480BA000
-#endif
-
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-
struct omap2_mcspi_platform_config {
unsigned int regs_offset;
};
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
-#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT 0
-#define MCSPI_PINDIR_D0_OUT_D1_IN 1
-
-#define OMAP3_MCSPI_MAX_FREQ 48000000
-#define SPI_WAIT_TIMEOUT 10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
- unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
- unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
- unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
- unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
- unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned int irqstatus; /* 0x18 */
- unsigned int irqenable; /* 0x1C */
- unsigned int wakeupenable; /* 0x20 */
- unsigned int syst; /* 0x24 */
- unsigned int modulctrl; /* 0x28 */
- struct mcspi_channel channel[4];
- /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
- /* channel1: 0x40 - 0x50, bus 0 & 1 */
- /* channel2: 0x54 - 0x64, bus 0 & 1 */
- /* channel3: 0x68 - 0x78, bus 0 */
-};
-
struct omap3_spi_priv {
-#ifndef CONFIG_DM_SPI
- struct spi_slave slave;
-#endif
struct mcspi *regs;
unsigned int cs;
unsigned int freq;
writel(conf, &priv->regs->modulctrl);
}
-#ifndef CONFIG_DM_SPI
-
-static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct omap3_spi_priv, slave);
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct omap3_spi_priv *priv = to_omap3_spi(slave);
-
- free(priv);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct omap3_spi_priv *priv = to_omap3_spi(slave);
-
- spi_reset(priv->regs);
-
- _omap3_spi_claim_bus(priv);
- _omap3_spi_set_wordlen(priv);
- _omap3_spi_set_mode(priv);
- _omap3_spi_set_speed(priv);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct omap3_spi_priv *priv = to_omap3_spi(slave);
-
- writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct omap3_spi_priv *priv;
- struct mcspi *regs;
-
- /*
- * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
- * with different number of chip selects (CS, channels):
- * McSPI1 has 4 CS (bus 0, cs 0 - 3)
- * McSPI2 has 2 CS (bus 1, cs 0 - 1)
- * McSPI3 has 2 CS (bus 2, cs 0 - 1)
- * McSPI4 has 1 CS (bus 3, cs 0)
- */
-
- switch (bus) {
- case 0:
- regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
- break;
-#ifdef OMAP3_MCSPI2_BASE
- case 1:
- regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
- break;
-#endif
-#ifdef OMAP3_MCSPI3_BASE
- case 2:
- regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
- break;
-#endif
-#ifdef OMAP3_MCSPI4_BASE
- case 3:
- regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
- break;
-#endif
- default:
- printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
- return NULL;
- }
-
- if (((bus == 0) && (cs > 3)) ||
- ((bus == 1) && (cs > 1)) ||
- ((bus == 2) && (cs > 1)) ||
- ((bus == 3) && (cs > 0))) {
- printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
- return NULL;
- }
-
- if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
- max_hz);
- return NULL;
- }
-
- if (mode > SPI_MODE_3) {
- printf("SPI error: unsupported SPI mode %i\n", mode);
- return NULL;
- }
-
- priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
- if (!priv) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
-
- priv->regs = regs;
- priv->cs = cs;
- priv->freq = max_hz;
- priv->mode = mode;
- priv->wordlen = priv->slave.wordlen;
-#if 0
- /* Please migrate to DM_SPI support for this feature. */
- priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
-#endif
-
- return &priv->slave;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct omap3_spi_priv *priv = to_omap3_spi(slave);
-
- return _spi_xfer(priv, bitlen, dout, din, flags);
-}
-
-#else
-
static int omap3_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
static int omap3_spi_probe(struct udevice *dev)
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
- struct omap2_mcspi_platform_config* data =
- (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
-
- priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
- if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
- priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
- else
- priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+ priv->regs = plat->regs;
+ priv->pin_dir = plat->pin_dir;
priv->wordlen = SPI_DEFAULT_WORDLEN;
spi_reset(priv->regs);
*/
};
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static struct omap2_mcspi_platform_config omap2_pdata = {
.regs_offset = 0,
};
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
};
+static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct omap2_mcspi_platform_config *data =
+ (struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
+ struct omap3_spi_plat *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
+
+ if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
+ plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+ else
+ plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+
+ return 0;
+}
+
static const struct udevice_id omap3_spi_ids[] = {
{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
{ }
};
-
+#endif
U_BOOT_DRIVER(omap3_spi) = {
.name = "omap3_spi",
.id = UCLASS_SPI,
+ .flags = DM_FLAG_PRE_RELOC,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap3_spi_ids,
+ .ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
+ .platdata_auto = sizeof(struct omap3_spi_plat),
+#endif
.probe = omap3_spi_probe,
.ops = &omap3_spi_ops,
- .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
+ .priv_auto = sizeof(struct omap3_spi_priv),
};
-#endif
projects / platform / kernel / u-boot.git / blobdiff