+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* Derived from drivers/spi/mpc8xxx_spi.c
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
+#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_KIRKWOOD
+#ifdef CONFIG_ARCH_KIRKWOOD
#include <asm/arch/mpp.h>
#endif
#include <asm/arch-mvebu/spi.h>
+struct mvebu_spi_dev {
+ bool is_errata_50mhz_ac;
+};
+
+struct mvebu_spi_plat {
+ struct kwspi_registers *spireg;
+ bool is_errata_50mhz_ac;
+};
+
+struct mvebu_spi_priv {
+ struct kwspi_registers *spireg;
+};
+
static void _spi_cs_activate(struct kwspi_registers *reg)
{
setbits_le32(®->ctrl, KWSPI_CSN_ACT);
return 0;
}
-#ifndef CONFIG_DM_SPI
-
-static struct kwspi_registers *spireg =
- (struct kwspi_registers *)MVEBU_SPI_BASE;
-
-#ifdef CONFIG_KIRKWOOD
-static u32 cs_spi_mpp_back[2];
-#endif
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
- struct spi_slave *slave;
- u32 data;
-#ifdef CONFIG_KIRKWOOD
- static const u32 kwspi_mpp_config[2][2] = {
- { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
- { MPP7_SPI_SCn, 0 } /* if cs != 0 */
- };
-#endif
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- slave = spi_alloc_slave_base(bus, cs);
- if (!slave)
- return NULL;
-
- writel(KWSPI_SMEMRDY, &spireg->ctrl);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
+ struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data, divider;
+ unsigned int spr, sppr;
- /* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
- data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
- data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
+ if (spi->max_hz && (hz > spi->max_hz)) {
+ debug("%s: limit speed to the max_hz of the bus %d\n",
+ __func__, spi->max_hz);
+ hz = spi->max_hz;
+ }
- /* program spi clock prescaller using max_hz */
- writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
- debug("data = 0x%08x\n", data);
+ /*
+ * Calculate spi clock prescaller using max_hz.
+ * SPPR is SPI Baud Rate Pre-selection, it holds bits 5 and 7:6 in
+ * SPI Interface Configuration Register;
+ * SPR is SPI Baud Rate Selection, it holds bits 3:0 in SPI Interface
+ * Configuration Register.
+ * The SPR together with the SPPR define the SPI CLK frequency as
+ * follows:
+ * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR))
+ */
+ divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz);
+ if (divider < 16) {
+ /* This is the easy case, divider is less than 16 */
+ spr = divider;
+ sppr = 0;
+
+ } else {
+ unsigned int two_pow_sppr;
+ /*
+ * Find the highest bit set in divider. This and the
+ * three next bits define SPR (apart from rounding).
+ * SPPR is then the number of zero bits that must be
+ * appended:
+ */
+ sppr = fls(divider) - 4;
- writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
- writel(KWSPI_IRQMASK, &spireg->irq_mask);
+ /*
+ * As SPR only has 4 bits, we have to round divider up
+ * to the next multiple of 2 ** sppr.
+ */
+ two_pow_sppr = 1 << sppr;
+ divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
-#ifdef CONFIG_KIRKWOOD
- /* program mpp registers to select SPI_CSn */
- kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
-#endif
+ /*
+ * recalculate sppr as rounding up divider might have
+ * increased it enough to change the position of the
+ * highest set bit. In this case the bit that now
+ * doesn't make it into SPR is 0, so there is no need to
+ * round again.
+ */
+ sppr = fls(divider) - 4;
+ spr = divider >> sppr;
- return slave;
-}
+ /*
+ * Now do range checking. SPR is constructed to have a
+ * width of 4 bits, so this is fine for sure. So we
+ * still need to check for sppr to fit into 3 bits:
+ */
+ if (sppr > 7)
+ return -EINVAL;
+ }
-void spi_free_slave(struct spi_slave *slave)
-{
-#ifdef CONFIG_KIRKWOOD
- kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
-#endif
- free(slave);
-}
+ data = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
-#if defined(CONFIG_SYS_KW_SPI_MPP)
-u32 spi_mpp_backup[4];
-#endif
+ /* program spi clock prescaler using max_hz */
+ writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
+ debug("data = 0x%08x\n", data);
-__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
-{
return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
{
-#if defined(CONFIG_SYS_KW_SPI_MPP)
- u32 config;
- u32 spi_mpp_config[4];
-
- config = CONFIG_SYS_KW_SPI_MPP;
-
- if (config & MOSI_MPP6)
- spi_mpp_config[0] = MPP6_SPI_MOSI;
- else
- spi_mpp_config[0] = MPP1_SPI_MOSI;
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data;
- if (config & SCK_MPP10)
- spi_mpp_config[1] = MPP10_SPI_SCK;
- else
- spi_mpp_config[1] = MPP2_SPI_SCK;
+ /*
+ * Erratum description: (Erratum NO. FE-9144572) The device
+ * SPI interface supports frequencies of up to 50 MHz.
+ * However, due to this erratum, when the device core clock is
+ * 250 MHz and the SPI interfaces is configured for 50MHz SPI
+ * clock and CPOL=CPHA=1 there might occur data corruption on
+ * reads from the SPI device.
+ * Erratum Workaround:
+ * Work in one of the following configurations:
+ * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
+ * Register".
+ * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
+ * Register" before setting the interface.
+ */
+ data = readl(®->timing1);
+ data &= ~KW_SPI_TMISO_SAMPLE_MASK;
- if (config & MISO_MPP11)
- spi_mpp_config[2] = MPP11_SPI_MISO;
+ if (CONFIG_SYS_TCLK == 250000000 &&
+ mode & SPI_CPOL &&
+ mode & SPI_CPHA)
+ data |= KW_SPI_TMISO_SAMPLE_2;
else
- spi_mpp_config[2] = MPP3_SPI_MISO;
-
- spi_mpp_config[3] = 0;
- spi_mpp_backup[3] = 0;
-
- /* set new spi mpp and save current mpp config */
- kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
-#endif
+ data |= KW_SPI_TMISO_SAMPLE_1;
- return board_spi_claim_bus(slave);
+ writel(data, ®->timing1);
}
-__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
-}
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data = readl(®->cfg);
-void spi_release_bus(struct spi_slave *slave)
-{
-#if defined(CONFIG_SYS_KW_SPI_MPP)
- kirkwood_mpp_conf(spi_mpp_backup, NULL);
-#endif
+ data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
- board_spi_release_bus(slave);
-}
+ if (mode & SPI_CPHA)
+ data |= KWSPI_CPHA;
+ if (mode & SPI_CPOL)
+ data |= KWSPI_CPOL;
+ if (mode & SPI_LSB_FIRST)
+ data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
-#ifndef CONFIG_SPI_CS_IS_VALID
-/*
- * you can define this function board specific
- * define above CONFIG in board specific config file and
- * provide the function in board specific src file
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && (cs == 0 || cs == 1);
-}
-#endif
+ writel(data, ®->cfg);
-void spi_init(void)
-{
-}
+ if (plat->is_errata_50mhz_ac)
+ mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
-void spi_cs_activate(struct spi_slave *slave)
-{
- _spi_cs_activate(spireg);
+ return 0;
}
-void spi_cs_deactivate(struct spi_slave *slave)
+static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- _spi_cs_deactivate(spireg);
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
+
+ return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+__attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
{
- return _spi_xfer(spireg, bitlen, dout, din, flags);
+ return 0;
}
-#else
-
-/* Here now the DM part */
-
-struct mvebu_spi_platdata {
- struct kwspi_registers *spireg;
-};
-
-struct mvebu_spi_priv {
- struct kwspi_registers *spireg;
-};
-
-static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
+static int mvebu_spi_claim_bus(struct udevice *dev)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
- struct kwspi_registers *reg = plat->spireg;
- u32 data;
-
- /* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
- data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
- data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
- /* program spi clock prescaler using max_hz */
- writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
- debug("data = 0x%08x\n", data);
+ /* Configure the chip-select in the CTRL register */
+ clrsetbits_le32(&plat->spireg->ctrl,
+ KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+ spi_chip_select(dev) << KWSPI_CS_SHIFT);
- return 0;
+ return mvebu_board_spi_claim_bus(dev);
}
-static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
+__attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
{
return 0;
}
-static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int mvebu_spi_release_bus(struct udevice *dev)
{
- struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
-
- return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
+ return mvebu_board_spi_release_bus(dev);
}
static int mvebu_spi_probe(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
writel(KWSPI_SMEMRDY, ®->ctrl);
return 0;
}
-static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+static int mvebu_spi_of_to_plat(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
+ const struct mvebu_spi_dev *drvdata =
+ (struct mvebu_spi_dev *)dev_get_driver_data(bus);
- plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
+ plat->spireg = dev_read_addr_ptr(bus);
+ plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
return 0;
}
static const struct dm_spi_ops mvebu_spi_ops = {
+ .claim_bus = mvebu_spi_claim_bus,
+ .release_bus = mvebu_spi_release_bus,
.xfer = mvebu_spi_xfer,
.set_speed = mvebu_spi_set_speed,
.set_mode = mvebu_spi_set_mode,
*/
};
+static const struct mvebu_spi_dev armada_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
+static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
+static const struct mvebu_spi_dev armada_375_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
+static const struct mvebu_spi_dev armada_380_spi_dev_data = {
+ .is_errata_50mhz_ac = true,
+};
+
static const struct udevice_id mvebu_spi_ids[] = {
- { .compatible = "marvell,armada-380-spi" },
- { .compatible = "marvell,armada-xp-spi" },
+ {
+ .compatible = "marvell,orion-spi",
+ .data = (ulong)&armada_spi_dev_data,
+ },
+ {
+ .compatible = "marvell,armada-375-spi",
+ .data = (ulong)&armada_375_spi_dev_data
+ },
+ {
+ .compatible = "marvell,armada-380-spi",
+ .data = (ulong)&armada_380_spi_dev_data
+ },
+ {
+ .compatible = "marvell,armada-xp-spi",
+ .data = (ulong)&armada_xp_spi_dev_data
+ },
{ }
};
.id = UCLASS_SPI,
.of_match = mvebu_spi_ids,
.ops = &mvebu_spi_ops,
- .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
- .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
+ .of_to_plat = mvebu_spi_of_to_plat,
+ .plat_auto = sizeof(struct mvebu_spi_plat),
+ .priv_auto = sizeof(struct mvebu_spi_priv),
.probe = mvebu_spi_probe,
};
-#endif
projects / platform / kernel / u-boot.git / blobdiff