#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
+#include <bootstage.h>
#include <div64.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
+#include <log.h>
#include <malloc.h>
#include <pch.h>
#include <pci.h>
#include <pci_ids.h>
#include <spi.h>
+#include <spi_flash.h>
#include <spi-mem.h>
+#include <spl.h>
+#include <asm/fast_spi.h>
#include <asm/io.h>
+#include <asm/mtrr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
#include "ich.h"
bool lockdown; /* lock down controller settings? */
ulong mmio_base; /* Base of MMIO registers */
pci_dev_t bdf; /* PCI address used by of-platdata */
+ bool hwseq; /* Use hardware sequencing (not s/w) */
};
static u8 ich_readb(struct ich_spi_priv *priv, int reg)
const uint32_t bbar_mask = 0x00ffff00;
uint32_t ichspi_bbar;
- minaddr &= bbar_mask;
- ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
- ichspi_bbar |= minaddr;
- ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+ if (ctlr->bbar) {
+ minaddr &= bbar_mask;
+ ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
+ ichspi_bbar |= minaddr;
+ ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+ }
}
/* @return 1 if the SPI flash supports the 33MHz speed */
struct ich_spi_priv *priv = dev_get_priv(dev);
u32 fdod, speed;
+ if (!CONFIG_IS_ENABLED(PCI))
+ return false;
/* Observe SPI Descriptor Component Section 0 */
dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
}
-static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+static int ich_spi_exec_op_swseq(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
struct udevice *bus = dev_get_parent(slave->dev);
struct ich_spi_platdata *plat = dev_get_platdata(bus);
return 0;
}
+/*
+ * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
+ * that the operation does not cross page boundary.
+ */
+static uint get_xfer_len(u32 offset, int len, int page_size)
+{
+ uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
+ uint bytes_left = ALIGN(offset, page_size) - offset;
+
+ if (bytes_left)
+ xfer_len = min(xfer_len, bytes_left);
+
+ return xfer_len;
+}
+
+/* Fill FDATAn FIFO in preparation for a write transaction */
+static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data,
+ uint len)
+{
+ memcpy(regs->fdata, data, len);
+}
+
+/* Drain FDATAn FIFO after a read transaction populates data */
+static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len)
+{
+ memcpy(dest, regs->fdata, len);
+}
+
+/* Fire up a transfer using the hardware sequencer */
+static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
+ uint offset, uint len)
+{
+ /* Make sure all W1C status bits get cleared */
+ u32 hsfsts;
+
+ hsfsts = readl(®s->hsfsts_ctl);
+ hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK);
+ hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE;
+
+ /* Set up transaction parameters */
+ hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT;
+ hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK;
+ hsfsts |= HSFSTS_FGO;
+
+ writel(offset, ®s->faddr);
+ writel(hsfsts, ®s->hsfsts_ctl);
+}
+
+static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset)
+{
+ ulong start;
+ u32 hsfsts;
+
+ start = get_timer(0);
+ do {
+ hsfsts = readl(®s->hsfsts_ctl);
+ if (hsfsts & HSFSTS_FCERR) {
+ debug("SPI transaction error at offset %x HSFSTS = %08x\n",
+ offset, hsfsts);
+ return -EIO;
+ }
+ if (hsfsts & HSFSTS_AEL)
+ return -EPERM;
+
+ if (hsfsts & HSFSTS_FDONE)
+ return 0;
+ } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
+
+ debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n",
+ offset, hsfsts, (uint)get_timer(start));
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing
+ *
+ * This waits until complete or timeout
+ *
+ * @regs: SPI registers
+ * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t)
+ * @offset: Offset to access
+ * @len: Number of bytes to transfer (can be 0)
+ * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error
+ * (AEL), -ETIMEDOUT on timeout
+ */
+static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle,
+ uint offset, uint len)
+{
+ start_hwseq_xfer(regs, hsfsts_cycle, offset, len);
+
+ return wait_for_hwseq_xfer(regs, offset);
+}
+
+static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(slave->dev);
+ struct udevice *bus = dev_get_parent(slave->dev);
+ struct ich_spi_priv *priv = dev_get_priv(bus);
+ struct fast_spi_regs *regs = priv->base;
+ uint page_size;
+ uint offset;
+ int cycle;
+ uint len;
+ bool out;
+ int ret;
+ u8 *buf;
+
+ offset = op->addr.val;
+ len = op->data.nbytes;
+
+ switch (op->cmd.opcode) {
+ case SPINOR_OP_RDID:
+ cycle = HSFSTS_CYCLE_RDID;
+ break;
+ case SPINOR_OP_READ_FAST:
+ cycle = HSFSTS_CYCLE_READ;
+ break;
+ case SPINOR_OP_PP:
+ cycle = HSFSTS_CYCLE_WRITE;
+ break;
+ case SPINOR_OP_WREN:
+ /* Nothing needs to be done */
+ return 0;
+ case SPINOR_OP_WRSR:
+ cycle = HSFSTS_CYCLE_WR_STATUS;
+ break;
+ case SPINOR_OP_RDSR:
+ cycle = HSFSTS_CYCLE_RD_STATUS;
+ break;
+ case SPINOR_OP_WRDI:
+ return 0; /* ignore */
+ case SPINOR_OP_BE_4K:
+ cycle = HSFSTS_CYCLE_4K_ERASE;
+ ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
+ return ret;
+ default:
+ debug("Unknown cycle %x\n", op->cmd.opcode);
+ return -EINVAL;
+ };
+
+ out = op->data.dir == SPI_MEM_DATA_OUT;
+ buf = out ? (u8 *)op->data.buf.out : op->data.buf.in;
+ page_size = flash->page_size ? : 256;
+
+ while (len) {
+ uint xfer_len = get_xfer_len(offset, len, page_size);
+
+ if (out)
+ fill_xfer_fifo(regs, buf, xfer_len);
+
+ ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len);
+ if (ret)
+ return ret;
+
+ if (!out)
+ drain_xfer_fifo(regs, buf, xfer_len);
+
+ offset += xfer_len;
+ buf += xfer_len;
+ len -= xfer_len;
+ }
+
+ return 0;
+}
+
+static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+ struct udevice *bus = dev_get_parent(slave->dev);
+ struct ich_spi_platdata *plat = dev_get_platdata(bus);
+ int ret;
+
+ bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
+ if (plat->hwseq)
+ ret = ich_spi_exec_op_hwseq(slave, op);
+ else
+ ret = ich_spi_exec_op_swseq(slave, op);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI);
+
+ return ret;
+}
+
+static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
+ uint *map_sizep, uint *offsetp)
+{
+ pci_dev_t spi_bdf;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(bus);
+
+ spi_bdf = pplat->devfn;
+#else
+ struct ich_spi_platdata *plat = dev_get_platdata(bus);
+
+ /*
+ * We cannot rely on plat->bdf being set up yet since this method can
+ * be called before the device is probed. Use the of-platdata directly
+ * instead.
+ */
+ spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
+#endif
+
+ return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp);
+}
+
+static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
+ uint *offsetp)
+{
+ struct udevice *bus = dev_get_parent(dev);
+
+ return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp);
+}
+
static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
{
unsigned int page_offset;
struct ich_spi_platdata *plat,
struct ich_spi_priv *ctlr)
{
+ if (spl_phase() == PHASE_TPL) {
+ struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
+ if (ret)
+ return ret;
+ }
+
ctlr->base = (void *)plat->mmio_base;
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = ctlr->base;
ctlr->preop = offsetof(struct ich9_spi_regs, preop);
ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
ctlr->pr = &ich9_spi->pr[0];
+ } else if (plat->ich_version == ICHV_APL) {
} else {
debug("ICH SPI: Unrecognised ICH version %d\n",
plat->ich_version);
return 0;
}
+static int ich_cache_bios_region(struct udevice *dev)
+{
+ ulong map_base;
+ uint map_size;
+ uint offset;
+ ulong base;
+ int ret;
+
+ ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
+ if (ret)
+ return ret;
+
+ /* Don't use WRBACK since we are not supposed to write to SPI flash */
+ base = SZ_4G - map_size;
+ mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
+ log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
+
+ return 0;
+}
+
static int ich_spi_probe(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
if (ret)
return ret;
- ret = ich_protect_lockdown(dev);
- if (ret)
- return ret;
-
+ if (spl_phase() == PHASE_TPL) {
+ /* Cache the BIOS to speed things up */
+ ret = ich_cache_bios_region(dev);
+ if (ret)
+ return ret;
+ } else {
+ ret = ich_protect_lockdown(dev);
+ if (ret)
+ return ret;
+ }
priv->cur_speed = priv->max_speed;
return 0;
/*
* Yes this controller can only write a small number of bytes at
- * once! The limit is typically 64 bytes.
+ * once! The limit is typically 64 bytes. For hardware sequencing a
+ * a loop is used to get around this.
*/
- slave->max_write_size = priv->databytes;
+ if (!plat->hwseq)
+ slave->max_write_size = priv->databytes;
/*
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
plat->ich_version = dev_get_driver_data(dev);
plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
- pch_get_spi_base(priv->pch, &plat->mmio_base);
+ if (plat->ich_version == ICHV_APL) {
+ plat->mmio_base = dm_pci_read_bar32(dev, 0);
+ } else {
+ /* SBASE is similar */
+ pch_get_spi_base(priv->pch, &plat->mmio_base);
+ }
+ /*
+ * Use an int so that the property is present in of-platdata even
+ * when false.
+ */
+ plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0);
#else
plat->ich_version = ICHV_APL;
plat->mmio_base = plat->dtplat.early_regs[0];
plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
+ plat->hwseq = plat->dtplat.intel_hardware_seq;
#endif
debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);
.set_speed = ich_spi_set_speed,
.set_mode = ich_spi_set_mode,
.mem_ops = &ich_controller_mem_ops,
+ .get_mmap = ich_get_mmap,
/*
* cs_info is not needed, since we require all chip selects to be
* in the device tree explicitly
static const struct udevice_id ich_spi_ids[] = {
{ .compatible = "intel,ich7-spi", ICHV_7 },
{ .compatible = "intel,ich9-spi", ICHV_9 },
+ { .compatible = "intel,fast-spi", ICHV_APL },
{ }
};
projects / platform / kernel / u-boot.git / blobdiff