common: Drop linux/bitops.h from common header

[platform/kernel/u-boot.git] / drivers / spi / ich.c

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 160ec37..7405062 100644 (file)
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -8,10 +8,12 @@
 #define LOG_CATEGORY   UCLASS_SPI
 
 #include <common.h>
+#include <bootstage.h>
 #include <div64.h>
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <log.h>
 #include <malloc.h>
 #include <pch.h>
 #include <pci.h>
@@ -19,8 +21,13 @@
 #include <spi.h>
 #include <spi_flash.h>
 #include <spi-mem.h>
+#include <spl.h>
 #include <asm/fast_spi.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
 
 #include "ich.h"
 
@@ -103,10 +110,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
        const uint32_t bbar_mask = 0x00ffff00;
        uint32_t ichspi_bbar;
 
-       minaddr &= bbar_mask;
-       ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
-       ichspi_bbar |= minaddr;
-       ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+       if (ctlr->bbar) {
+               minaddr &= bbar_mask;
+               ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
+               ichspi_bbar |= minaddr;
+               ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+       }
 }
 
 /* @return 1 if the SPI flash supports the 33MHz speed */
@@ -115,6 +124,8 @@ static bool ich9_can_do_33mhz(struct udevice *dev)
        struct ich_spi_priv *priv = dev_get_priv(dev);
        u32 fdod, speed;
 
+       if (!CONFIG_IS_ENABLED(PCI))
+               return false;
        /* Observe SPI Descriptor Component Section 0 */
        dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
 
@@ -555,16 +566,8 @@ static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
                return 0;  /* ignore */
        case SPINOR_OP_BE_4K:
                cycle = HSFSTS_CYCLE_4K_ERASE;
-               while (len) {
-                       uint xfer_len = 0x1000;
-
-                       ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
-                       if (ret)
-                               return ret;
-                       offset += xfer_len;
-                       len -= xfer_len;
-               }
-               return 0;
+               ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
+               return ret;
        default:
                debug("Unknown cycle %x\n", op->cmd.opcode);
                return -EINVAL;
@@ -706,6 +709,15 @@ static int ich_init_controller(struct udevice *dev,
                               struct ich_spi_platdata *plat,
                               struct ich_spi_priv *ctlr)
 {
+       if (spl_phase() == PHASE_TPL) {
+               struct ich_spi_platdata *plat = dev_get_platdata(dev);
+               int ret;
+
+               ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
+               if (ret)
+                       return ret;
+       }
+
        ctlr->base = (void *)plat->mmio_base;
        if (plat->ich_version == ICHV_7) {
                struct ich7_spi_regs *ich7_spi = ctlr->base;
@@ -736,6 +748,7 @@ static int ich_init_controller(struct udevice *dev,
                ctlr->preop = offsetof(struct ich9_spi_regs, preop);
                ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
                ctlr->pr = &ich9_spi->pr[0];
+       } else if (plat->ich_version == ICHV_APL) {
        } else {
                debug("ICH SPI: Unrecognised ICH version %d\n",
                      plat->ich_version);
@@ -754,6 +767,26 @@ static int ich_init_controller(struct udevice *dev,
        return 0;
 }
 
+static int ich_cache_bios_region(struct udevice *dev)
+{
+       ulong map_base;
+       uint map_size;
+       uint offset;
+       ulong base;
+       int ret;
+
+       ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
+       if (ret)
+               return ret;
+
+       /* Don't use WRBACK since we are not supposed to write to SPI flash */
+       base = SZ_4G - map_size;
+       mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
+       log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
+
+       return 0;
+}
+
 static int ich_spi_probe(struct udevice *dev)
 {
        struct ich_spi_platdata *plat = dev_get_platdata(dev);
@@ -764,10 +797,16 @@ static int ich_spi_probe(struct udevice *dev)
        if (ret)
                return ret;
 
-       ret = ich_protect_lockdown(dev);
-       if (ret)
-               return ret;
-
+       if (spl_phase() == PHASE_TPL) {
+               /* Cache the BIOS to speed things up */
+               ret = ich_cache_bios_region(dev);
+               if (ret)
+                       return ret;
+       } else {
+               ret = ich_protect_lockdown(dev);
+               if (ret)
+                       return ret;
+       }
        priv->cur_speed = priv->max_speed;
 
        return 0;
@@ -838,7 +877,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 
        plat->ich_version = dev_get_driver_data(dev);
        plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
-       pch_get_spi_base(priv->pch, &plat->mmio_base);
+       if (plat->ich_version == ICHV_APL) {
+               plat->mmio_base = dm_pci_read_bar32(dev, 0);
+       } else  {
+               /* SBASE is similar */
+               pch_get_spi_base(priv->pch, &plat->mmio_base);
+       }
        /*
         * Use an int so that the property is present in of-platdata even
         * when false.
@@ -876,6 +920,7 @@ static const struct dm_spi_ops ich_spi_ops = {
 static const struct udevice_id ich_spi_ids[] = {
        { .compatible = "intel,ich7-spi", ICHV_7 },
        { .compatible = "intel,ich9-spi", ICHV_9 },
+       { .compatible = "intel,fast-spi", ICHV_APL },
        { }
 };