common: Drop linux/bitops.h from common header

[platform/kernel/u-boot.git] / drivers / spi / ich.c

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 0cd073c..7405062 100644 (file)
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -8,10 +8,12 @@
 #define LOG_CATEGORY   UCLASS_SPI
 
 #include <common.h>
+#include <bootstage.h>
 #include <div64.h>
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <log.h>
 #include <malloc.h>
 #include <pch.h>
 #include <pci.h>
@@ -23,6 +25,8 @@
 #include <asm/fast_spi.h>
 #include <asm/io.h>
 #include <asm/mtrr.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 #include <linux/sizes.h>
 
 #include "ich.h"
@@ -106,10 +110,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
        const uint32_t bbar_mask = 0x00ffff00;
        uint32_t ichspi_bbar;
 
-       minaddr &= bbar_mask;
-       ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
-       ichspi_bbar |= minaddr;
-       ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+       if (ctlr->bbar) {
+               minaddr &= bbar_mask;
+               ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
+               ichspi_bbar |= minaddr;
+               ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
+       }
 }
 
 /* @return 1 if the SPI flash supports the 33MHz speed */
@@ -560,16 +566,8 @@ static int ich_spi_exec_op_hwseq(struct spi_slave *slave,
                return 0;  /* ignore */
        case SPINOR_OP_BE_4K:
                cycle = HSFSTS_CYCLE_4K_ERASE;
-               while (len) {
-                       uint xfer_len = 0x1000;
-
-                       ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
-                       if (ret)
-                               return ret;
-                       offset += xfer_len;
-                       len -= xfer_len;
-               }
-               return 0;
+               ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0);
+               return ret;
        default:
                debug("Unknown cycle %x\n", op->cmd.opcode);
                return -EINVAL;
@@ -750,6 +748,7 @@ static int ich_init_controller(struct udevice *dev,
                ctlr->preop = offsetof(struct ich9_spi_regs, preop);
                ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
                ctlr->pr = &ich9_spi->pr[0];
+       } else if (plat->ich_version == ICHV_APL) {
        } else {
                debug("ICH SPI: Unrecognised ICH version %d\n",
                      plat->ich_version);
@@ -878,7 +877,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 
        plat->ich_version = dev_get_driver_data(dev);
        plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
-       pch_get_spi_base(priv->pch, &plat->mmio_base);
+       if (plat->ich_version == ICHV_APL) {
+               plat->mmio_base = dm_pci_read_bar32(dev, 0);
+       } else  {
+               /* SBASE is similar */
+               pch_get_spi_base(priv->pch, &plat->mmio_base);
+       }
        /*
         * Use an int so that the property is present in of-platdata even
         * when false.
@@ -916,6 +920,7 @@ static const struct dm_spi_ops ich_spi_ops = {
 static const struct udevice_id ich_spi_ids[] = {
        { .compatible = "intel,ich7-spi", ICHV_7 },
        { .compatible = "intel,ich9-spi", ICHV_9 },
+       { .compatible = "intel,fast-spi", ICHV_APL },
        { }
 };