#include <linux/sizes.h>
#include <dm.h>
#include <errno.h>
+#include <watchdog.h>
#include "fsl_qspi.h"
DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK 0x00ffffff
+#define OFFSET_BITS_MASK GENMASK(23, 0)
#define FLASH_STATUS_WEL 0x02
#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* default SCK frequency, unit: HZ */
#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
/* Enable the module again (enable the DDR too) */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
- reg |= (1 << 29);
+ reg |= BIT(29);
qspi_write32(priv->flags, ®s->mcr, reg);
}
to_or_from = priv->sf_addr + priv->cur_amba_base;
while (len > 0) {
+ WATCHDOG_RESET();
+
qspi_write32(priv->flags, ®s->sfar, to_or_from);
size = (len > RX_BUFFER_SIZE) ?
status_reg = 0;
while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
+ WATCHDOG_RESET();
+
qspi_write32(priv->flags, ®s->ipcr,
(SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
#else
static int fsl_qspi_child_pre_probe(struct udevice *dev)
{
- struct spi_slave *slave = dev_get_parentdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
slave->max_write_size = TX_BUFFER_SIZE;