/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#include <phy.h>
/* Default UTBIPAR SMI address */
#ifndef CONFIG_UTBIPAR_INIT_TBIPA
static struct eth_device *devlist[MAXCONTROLLERS];
-u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
-void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
-
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
uec_t *uec_regs;
return 0;
}
-static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
+static int uec_set_mac_if_mode(uec_private_t *uec,
+ phy_interface_t if_mode, int speed)
{
- enet_interface_e enet_if_mode;
+ phy_interface_t enet_if_mode;
uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
- switch (enet_if_mode) {
- case ENET_100_MII:
- case ENET_10_MII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- break;
- case ENET_1000_GMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- break;
- case ENET_1000_TBI:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= UPSMR_TBIM;
- break;
- case ENET_1000_RTBI:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= (UPSMR_RPM | UPSMR_TBIM);
- break;
- case ENET_1000_RGMII_RXID:
- case ENET_1000_RGMII_ID:
- case ENET_1000_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= UPSMR_RPM;
- break;
- case ENET_100_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= UPSMR_RPM;
- break;
- case ENET_10_RGMII:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= (UPSMR_RPM | UPSMR_R10M);
- break;
- case ENET_100_RMII:
+ switch (speed) {
+ case SPEED_10:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= UPSMR_RMM;
+ switch (enet_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ upsmr |= (UPSMR_RPM | UPSMR_R10M);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ upsmr |= (UPSMR_R10M | UPSMR_RMM);
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
break;
- case ENET_10_RMII:
+ case SPEED_100:
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- upsmr |= (UPSMR_R10M | UPSMR_RMM);
+ switch (enet_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ upsmr |= UPSMR_RPM;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ upsmr |= UPSMR_RMM;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
break;
- case ENET_1000_SGMII:
+ case SPEED_1000:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- upsmr |= UPSMR_SGMM;
+ switch (enet_if_mode) {
+ case PHY_INTERFACE_MODE_GMII:
+ break;
+ case PHY_INTERFACE_MODE_TBI:
+ upsmr |= UPSMR_TBIM;
+ break;
+ case PHY_INTERFACE_MODE_RTBI:
+ upsmr |= (UPSMR_RPM | UPSMR_TBIM);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII:
+ upsmr |= UPSMR_RPM;
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ upsmr |= UPSMR_SGMM;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
break;
default:
return -EINVAL;
break;
}
+
out_be32(&uec_regs->maccfg2, maccfg2);
out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev,
- enet_interface_e mode);
+ phy_interface_t mode, int speed);
uec_regs = uec->uec_regs;
if (mii_info->link) {
}
if (mii_info->speed != uec->oldspeed) {
+ phy_interface_t mode =
+ uec->uec_info->enet_interface_type;
if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
switch (mii_info->speed) {
- case 1000:
+ case SPEED_1000:
break;
- case 100:
+ case SPEED_100:
printf ("switching to rgmii 100\n");
- /* change phy to rgmii 100 */
- change_phy_interface_mode(dev,
- ENET_100_RGMII);
- /* change the MAC interface mode */
- uec_set_mac_if_mode(uec,ENET_100_RGMII);
+ mode = PHY_INTERFACE_MODE_RGMII;
break;
- case 10:
+ case SPEED_10:
printf ("switching to rgmii 10\n");
- /* change phy to rgmii 10 */
- change_phy_interface_mode(dev,
- ENET_10_RGMII);
- /* change the MAC interface mode */
- uec_set_mac_if_mode(uec,ENET_10_RGMII);
+ mode = PHY_INTERFACE_MODE_RGMII;
break;
default:
printf("%s: Ack,Speed(%d)is illegal\n",
}
}
+ /* change phy */
+ change_phy_interface_mode(dev, mode, mii_info->speed);
+ /* change the MAC interface mode */
+ uec_set_mac_if_mode(uec, mode, mii_info->speed);
+
printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
uec->oldspeed = mii_info->speed;
}
{
uec_private_t *uec = (uec_private_t *)dev->priv;
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /*
+ * QE12 is muxed with LBCTL, it needs to be released for enabling
+ * LBCTL signal for LBC usage.
+ */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Adjust the interface according to speed */
adjust_link(dev);
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/*
* Find a device index from the devlist by name
* Returns:
* The index where the device is located, -1 on error
*/
-static int uec_miiphy_find_dev_by_name(char *devname)
+static int uec_miiphy_find_dev_by_name(const char *devname)
{
int i;
* Returns:
* 0 on success
*/
-static int uec_miiphy_read(char *devname, unsigned char addr,
+static int uec_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
int devindex = 0;
* Returns:
* 0 on success
*/
-static int uec_miiphy_write(char *devname, unsigned char addr,
+static int uec_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int devindex = 0;
int num_threads_tx;
int num_threads_rx;
u32 utbipar;
- enet_interface_e enet_interface;
u32 length;
u32 align;
qe_bd_t *bd;
out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
/* Setup MAC interface mode */
- uec_set_mac_if_mode(uec, uec_info->enet_interface);
+ uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
/* Setup MII management base */
#ifndef CONFIG_eTSEC_MDIO_BUS
/* Setup UTBIPAR */
utbipar = in_be32(&uec_regs->utbipar);
utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
- enet_interface = uec->uec_info->enet_interface;
/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
* This frees up the remaining SMI addresses for use.
out_be32(&uec_regs->utbipar, utbipar);
/* Configure the TBI for SGMII operation */
- if (uec->uec_info->enet_interface == ENET_1000_SGMII) {
+ if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
+ (uec->uec_info->speed == SPEED_1000)) {
uec_write_phy_reg(uec->dev, uec_regs->utbipar,
ENET_TBI_MII_ANA, TBIANA_SETTINGS);
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
i = 50;
do {
err = curphy->read_status(uec->mii_info);
+ if (!(((i-- > 0) && !uec->mii_info->link) || err))
+ break;
udelay(100000);
- } while (((i-- > 0) && !uec->mii_info->link) || err);
+ } while (1);
+
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /* QE12 needs to be released for enabling LBCTL signal*/
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
+ adjust_link(dev);
uec->the_first_run = 1;
}
uec->uec_info = uec_info;
uec->dev = dev;
- sprintf(dev->name, "FSL UEC%d", uec_info->uf_info.ucc_num);
+ sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
dev->iobase = 0;
dev->priv = (void *)uec;
dev->init = uec_init;
return err;
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
#endif
projects / platform / kernel / u-boot.git / blobdiff