+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
+#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/immap_qe.h>
#include <fsl_qe.h>
+#include <mmc.h>
+#include <u-boot/crc.h>
+
#ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h>
#endif
-
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#include <mmc.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
-qe_map_t *qe_immr = NULL;
+qe_map_t *qe_immr;
#ifdef CONFIG_QE
static qe_snum_t snums[QE_NUM_OF_SNUM];
#endif
u32 cecr;
if (cmd == QE_RESET) {
- out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
+ out_be32(&qe_immr->cp.cecr, (u32)(cmd | QE_CR_FLG));
} else {
out_be32(&qe_immr->cp.cecdr, cmd_data);
out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
- ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
+ ((u32)mcn << QE_CR_PROTOCOL_SHIFT) | cmd));
}
/* Wait for the QE_CR_FLG to clear */
do {
cecr = in_be32(&qe_immr->cp.cecr);
} while (cecr & QE_CR_FLG);
-
- return;
}
#ifdef CONFIG_QE
if (off != 0)
gd->arch.mp_alloc_base += (align - off);
- if ((off = size & align_mask) != 0)
+ off = size & align_mask;
+ if (off != 0)
size += (align - off);
if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
gd->arch.mp_alloc_base = savebase;
- printf("%s: ran out of ram.\n", __FUNCTION__);
+ printf("%s: ran out of ram.\n", __func__);
}
retloc = gd->arch.mp_alloc_base;
#ifdef CONFIG_QE
static void qe_sdma_init(void)
{
- volatile sdma_t *p;
- uint sdma_buffer_base;
+ sdma_t *p;
+ uint sdma_buffer_base;
- p = (volatile sdma_t *)&qe_immr->sdma;
+ p = (sdma_t *)&qe_immr->sdma;
/* All of DMA transaction in bus 1 */
out_be32(&p->sdaqr, 0);
*/
static u8 thread_snum[] = {
/* Evthreads 16-29 are not supported in MPC8309 */
-#if !defined(CONFIG_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0x34, 0x35,
-#endif
0x88, 0x89, 0x98, 0x99,
0xa8, 0xa9, 0xb8, 0xb9,
0xc8, 0xc9, 0xd8, 0xd9,
}
}
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+ enum boot_src src = get_boot_src();
+
+ /* Init the QE IMMR base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ /*
+ * Upload microcode to IRAM for those SOCs
+ * which do not have ROM in QE.
+ */
+ qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE));
+
+ /* enable the microcode in IRAM */
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ }
+
+ gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+ gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+ qe_sdma_init();
+ qe_snums_init();
+}
+#else
void qe_init(uint qe_base)
{
/* Init the QE IMMR base */
qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
/* enable the microcode in IRAM */
- out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
#endif
gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
qe_snums_init();
}
#endif
+#endif
#ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+ enum boot_src src = get_boot_src();
+
+ qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+ if (src == BOOT_SOURCE_IFC_NOR)
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE);
+
+ if (src == BOOT_SOURCE_QSPI_NOR)
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
+ CFG_SYS_FSL_QSPI_BASE);
+
+ if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+ dev, blk, cnt);
+ mmc_init(mmc);
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+ addr);
+ }
+ }
+ if (!u_qe_upload_firmware(addr))
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ if (src == BOOT_SOURCE_SD_MMC)
+ free(addr);
+}
+#else
void u_qe_init(void)
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
- free(addr);
printf("\nMMC cannot find device for ucode\n");
} else {
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512);
}
#endif
if (!u_qe_upload_firmware(addr))
#endif
}
#endif
+#endif
#ifdef CONFIG_U_QE
void u_qe_resume(void)
void qe_reset(void)
{
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
- (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+ (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
#ifdef CONFIG_QE
u32 cecr;
out_be32(&qe_immr->cp.cecdr, para_ram_base);
- out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
+ out_be32(&qe_immr->cp.cecr, ((u32)snum << QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
| QE_CR_FLG | QE_ASSIGN_PAGE);
/* Wait for the QE_CR_FLG to clear */
do {
cecr = in_be32(&qe_immr->cp.cecr);
- } while (cecr & QE_CR_FLG );
-
- return;
+ } while (cecr & QE_CR_FLG);
}
#endif
/*
* brg: 0~15 as BRG1~BRG16
- rate: baud rate
+ * rate: baud rate
* BRG input clock comes from the BRGCLK (internal clock generated from
- the QE clock, it is one-half of the QE clock), If need the clock source
- from CLKn pin, we have te change the function.
+ * the QE clock, it is one-half of the QE clock), If need the clock source
+ * from CLKn pin, we have te change the function.
*/
#define BRG_CLK (gd->arch.brg_clk)
#ifdef CONFIG_QE
int qe_set_brg(uint brg, uint rate)
{
- volatile uint *bp;
- u32 divisor;
- int div16 = 0;
+ uint *bp;
+ u32 divisor;
+ u32 val;
+ int div16 = 0;
if (brg >= QE_NUM_OF_BRGS)
return -EINVAL;
+
bp = (uint *)&qe_immr->brg.brgc1;
bp += brg;
divisor /= 16;
}
- *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
- __asm__ __volatile__("sync");
+ /* CHECK TODO */
+ /*
+ * was
+ * *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+ * __asm__ __volatile__("sync");
+ */
- if (div16) {
- *bp |= QE_BRGC_DIV16;
- __asm__ __volatile__("sync");
- }
+ val = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+ if (div16)
+ val |= QE_BRGC_DIV16;
+
+ out_be32(bp, val);
return 0;
}
#endif
-/* Set ethernet MII clock master
-*/
+/* Set ethernet MII clock master */
int qe_set_mii_clk_src(int ucc_num)
{
u32 cmxgcr;
/* check if the UCC number is in range. */
- if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
- printf("%s: ucc num not in ranges\n", __FUNCTION__);
+ if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
+ printf("%s: ucc num not in ranges\n", __func__);
return -EINVAL;
}
cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
- cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
+ cmxgcr |= (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
return 0;
* the actual uploading of the microcode.
*/
static void qe_upload_microcode(const void *base,
- const struct qe_microcode *ucode)
+ const struct qe_microcode *ucode)
{
const u32 *code = base + be32_to_cpu(ucode->code_offset);
unsigned int i;
/*
* Upload a microcode to the I-RAM at a specific address.
*
- * See docs/README.qe_firmware for information on QE microcode uploading.
+ * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
+ * information on QE microcode uploading.
*
* Currently, only version 1 is supported, so the 'version' field must be
* set to 1.
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
}
/* Validate some of the fields */
- if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+ if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
printf("Invalid data\n");
return -EINVAL;
}
* function isn't available unless you turn on JFFS support.
*/
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
- if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
+ if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
printf("Firmware CRC is invalid\n");
return -EIO;
}
*/
if (!firmware->split) {
out_be16(&qe_immr->cp.cercr,
- in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+ in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
}
if (firmware->soc.model)
printf("Firmware '%s' for %u V%u.%u\n",
- firmware->id, be16_to_cpu(firmware->soc.model),
+ firmware->id, be16_to_cpu(firmware->soc.model),
firmware->soc.major, firmware->soc.minor);
else
printf("Firmware '%s'\n", firmware->id);
strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
qe_firmware_info.extended_modes = firmware->extended_modes;
memcpy(qe_firmware_info.vtraps, firmware->vtraps,
- sizeof(firmware->vtraps));
+ sizeof(firmware->vtraps));
qe_firmware_uploaded = 1;
/* Loop through each microcode. */
/*
* Upload a microcode to the I-RAM at a specific address.
*
- * See docs/README.qe_firmware for information on QE microcode uploading.
+ * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
+ * information on QE microcode uploading.
*
* Currently, only version 1 is supported, so the 'version' field must be
* set to 1.
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
}
/* Validate some of the fields */
- if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+ if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
printf("Invalid data\n");
return -EINVAL;
}
const u32 *code;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_PPC
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#else
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#endif
#endif
return qe_firmware_uploaded ? &qe_firmware_info : NULL;
}
-static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong addr;
return cmd_usage(cmdtp);
if (strcmp(argv[1], "fw") == 0) {
- addr = simple_strtoul(argv[2], NULL, 16);
+ addr = hextoul(argv[2], NULL);
if (!addr) {
printf("Invalid address\n");
*/
if (argc > 3) {
- ulong length = simple_strtoul(argv[3], NULL, 16);
- struct qe_firmware *firmware = (void *) addr;
+ ulong length = hextoul(argv[3], NULL);
+ struct qe_firmware *firmware = (void *)addr;
if (length != be32_to_cpu(firmware->header.length)) {
printf("Length mismatch\n");
}
}
- return qe_upload_firmware((const struct qe_firmware *) addr);
+ return qe_upload_firmware((const struct qe_firmware *)addr);
}
return cmd_usage(cmdtp);
U_BOOT_CMD(
qe, 4, 0, qe_cmd,
"QUICC Engine commands",
- "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
- "the QE,\n"
+ "fw <addr> [<length>] - Upload firmware binary at address <addr> to the QE,\n"
"\twith optional length <length> verification."
);
projects / platform / kernel / u-boot.git / blobdiff