Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / drivers / pinctrl / renesas / pfc-r8a77995.c

diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index ed67858..724cf4a 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -290,7 +290,7 @@
 #define IP10_23_20     FM(SSI_SDATA4_A)        FM(HTX0)                FM(SCL2_A)              FM(CAN1_RX_B)   F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_27_24     FM(SSI_WS4_A)           FM(HRX0)                FM(SDA2_A)              FM(CAN1_TX_B)   F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_31_28     FM(SCL1)                FM(CTS1_N)              F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0       FM(SDA1)                FM(RTS1_N_TANS)         F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0       FM(SDA1)                FM(RTS1_N)              F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP11_7_4       FM(MSIOF1_SCK)          FM(AVB0_AVTP_PPS_B)     F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP11_11_8      FM(MSIOF1_TXD)          FM(AVB0_AVTP_CAPTURE_B) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP11_15_12     FM(MSIOF1_RXD)          FM(AVB0_AVTP_MATCH_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -301,7 +301,7 @@
 
 /* IPSRx */            /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */         /* 4 */                 /* 5 */         /* 6  - F */
 #define IP12_3_0       FM(RX1_A)               FM(CTS0_N)              FM(TPU0TO0_B)           F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4       FM(TX1_A)               FM(RTS0_N_TANS)         FM(TPU0TO1_B)           F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4       FM(TX1_A)               FM(RTS0_N)              FM(TPU0TO1_B)           F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_11_8      FM(SCK2)                FM(MSIOF1_SS1)          FM(TPU0TO3_B)           F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_15_12     FM(TPU0TO0_A)           FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_19_16     FM(TPU0TO1_A)           FM(AVB0_AVTP_MATCH_A)   FM(HRTS0_N)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -860,7 +860,7 @@ static const u16 pinmux_data[] = {
 
        /* IPSR11 */
        PINMUX_IPSR_GPSR(IP11_3_0,      SDA1),
-       PINMUX_IPSR_GPSR(IP11_3_0,      RTS1_N_TANS),
+       PINMUX_IPSR_GPSR(IP11_3_0,      RTS1_N),
 
        PINMUX_IPSR_GPSR(IP11_7_4,      MSIOF1_SCK),
        PINMUX_IPSR_MSEL(IP11_7_4,      AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
@@ -895,7 +895,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP12_3_0,      TPU0TO0_B),
 
        PINMUX_IPSR_MSEL(IP12_7_4,      TX1_A, SEL_SCIF1_0),
-       PINMUX_IPSR_GPSR(IP12_7_4,      RTS0_N_TANS),
+       PINMUX_IPSR_GPSR(IP12_7_4,      RTS0_N),
        PINMUX_IPSR_GPSR(IP12_7_4,      TPU0TO1_B),
 
        PINMUX_IPSR_GPSR(IP12_11_8,     SCK2),
@@ -1707,7 +1707,7 @@ static const unsigned int scif0_ctrl_pins[] = {
        RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
 };
 static const unsigned int scif0_ctrl_mux[] = {
-       RTS0_N_TANS_MARK, CTS0_N_MARK,
+       RTS0_N_MARK, CTS0_N_MARK,
 };
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_a_pins[] = {
@@ -1743,7 +1743,7 @@ static const unsigned int scif1_ctrl_pins[] = {
        RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
 };
 static const unsigned int scif1_ctrl_mux[] = {
-       RTS1_N_TANS_MARK, CTS1_N_MARK,
+       RTS1_N_MARK, CTS1_N_MARK,
 };
 
 /* - SCIF2 ------------------------------------------------------------------ */
@@ -2377,7 +2377,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 #define F_(x, y)       FN_##y
 #define FM(x)          FN_##x
-       { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+       { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -2409,9 +2409,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_0_3_FN,      GPSR0_3,
                GP_0_2_FN,      GPSR0_2,
                GP_0_1_FN,      GPSR0_1,
-               GP_0_0_FN,      GPSR0_0, }
+               GP_0_0_FN,      GPSR0_0, ))
        },
-       { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+       { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
                GP_1_31_FN,     GPSR1_31,
                GP_1_30_FN,     GPSR1_30,
                GP_1_29_FN,     GPSR1_29,
@@ -2443,9 +2443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_1_3_FN,      GPSR1_3,
                GP_1_2_FN,      GPSR1_2,
                GP_1_1_FN,      GPSR1_1,
-               GP_1_0_FN,      GPSR1_0, }
+               GP_1_0_FN,      GPSR1_0, ))
        },
-       { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+       { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
                GP_2_31_FN,     GPSR2_31,
                GP_2_30_FN,     GPSR2_30,
                GP_2_29_FN,     GPSR2_29,
@@ -2477,9 +2477,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_2_3_FN,      GPSR2_3,
                GP_2_2_FN,      GPSR2_2,
                GP_2_1_FN,      GPSR2_1,
-               GP_2_0_FN,      GPSR2_0, }
+               GP_2_0_FN,      GPSR2_0, ))
        },
-       { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+       { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -2511,9 +2511,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_3_3_FN,      GPSR3_3,
                GP_3_2_FN,      GPSR3_2,
                GP_3_1_FN,      GPSR3_1,
-               GP_3_0_FN,      GPSR3_0, }
+               GP_3_0_FN,      GPSR3_0, ))
        },
-       { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+       { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
                GP_4_31_FN,     GPSR4_31,
                GP_4_30_FN,     GPSR4_30,
                GP_4_29_FN,     GPSR4_29,
@@ -2545,9 +2545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_4_3_FN,      GPSR4_3,
                GP_4_2_FN,      GPSR4_2,
                GP_4_1_FN,      GPSR4_1,
-               GP_4_0_FN,      GPSR4_0, }
+               GP_4_0_FN,      GPSR4_0, ))
        },
-       { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+       { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -2579,9 +2579,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_5_3_FN,      GPSR5_3,
                GP_5_2_FN,      GPSR5_2,
                GP_5_1_FN,      GPSR5_1,
-               GP_5_0_FN,      GPSR5_0, }
+               GP_5_0_FN,      GPSR5_0, ))
        },
-       { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+       { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
                0, 0,
                0, 0,
                0, 0,
@@ -2613,14 +2613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_6_3_FN,      GPSR6_3,
                GP_6_2_FN,      GPSR6_2,
                GP_6_1_FN,      GPSR6_1,
-               GP_6_0_FN,      GPSR6_0, }
+               GP_6_0_FN,      GPSR6_0, ))
        },
 #undef F_
 #undef FM
 
 #define F_(x, y)       x,
 #define FM(x)          FN_##x,
-       { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+       { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
                IP0_31_28
                IP0_27_24
                IP0_23_20
@@ -2628,9 +2628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP0_15_12
                IP0_11_8
                IP0_7_4
-               IP0_3_0 }
+               IP0_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+       { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
                IP1_31_28
                IP1_27_24
                IP1_23_20
@@ -2638,9 +2638,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP1_15_12
                IP1_11_8
                IP1_7_4
-               IP1_3_0 }
+               IP1_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+       { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
                IP2_31_28
                IP2_27_24
                IP2_23_20
@@ -2648,9 +2648,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP2_15_12
                IP2_11_8
                IP2_7_4
-               IP2_3_0 }
+               IP2_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+       { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
                IP3_31_28
                IP3_27_24
                IP3_23_20
@@ -2658,9 +2658,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP3_15_12
                IP3_11_8
                IP3_7_4
-               IP3_3_0 }
+               IP3_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+       { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
                IP4_31_28
                IP4_27_24
                IP4_23_20
@@ -2668,9 +2668,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP4_15_12
                IP4_11_8
                IP4_7_4
-               IP4_3_0 }
+               IP4_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+       { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
                IP5_31_28
                IP5_27_24
                IP5_23_20
@@ -2678,9 +2678,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP5_15_12
                IP5_11_8
                IP5_7_4
-               IP5_3_0 }
+               IP5_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+       { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
                IP6_31_28
                IP6_27_24
                IP6_23_20
@@ -2688,9 +2688,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP6_15_12
                IP6_11_8
                IP6_7_4
-               IP6_3_0 }
+               IP6_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+       { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
                IP7_31_28
                IP7_27_24
                IP7_23_20
@@ -2698,9 +2698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP7_15_12
                IP7_11_8
                IP7_7_4
-               IP7_3_0 }
+               IP7_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+       { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
                IP8_31_28
                IP8_27_24
                IP8_23_20
@@ -2708,9 +2708,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP8_15_12
                IP8_11_8
                IP8_7_4
-               IP8_3_0 }
+               IP8_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+       { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
                IP9_31_28
                IP9_27_24
                IP9_23_20
@@ -2718,9 +2718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP9_15_12
                IP9_11_8
                IP9_7_4
-               IP9_3_0 }
+               IP9_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+       { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
                IP10_31_28
                IP10_27_24
                IP10_23_20
@@ -2728,9 +2728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP10_15_12
                IP10_11_8
                IP10_7_4
-               IP10_3_0 }
+               IP10_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+       { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
                IP11_31_28
                IP11_27_24
                IP11_23_20
@@ -2738,9 +2738,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP11_15_12
                IP11_11_8
                IP11_7_4
-               IP11_3_0 }
+               IP11_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+       { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
                IP12_31_28
                IP12_27_24
                IP12_23_20
@@ -2748,9 +2748,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP12_15_12
                IP12_11_8
                IP12_7_4
-               IP12_3_0 }
+               IP12_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+       { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
                /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2758,7 +2758,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                /* IP13_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                IP13_7_4
-               IP13_3_0 }
+               IP13_3_0 ))
        },
 #undef F_
 #undef FM
@@ -2766,8 +2766,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 #define F_(x, y)       x,
 #define FM(x)          FN_##x,
        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
-                            1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
-                            1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
+                            GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
+                                  1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
+                            GROUP(
                /* RESERVED 31 */
                0, 0,
                MOD_SEL0_30
@@ -2795,11 +2796,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL0_3
                MOD_SEL0_2
                MOD_SEL0_1
-               MOD_SEL0_0 }
+               MOD_SEL0_0 ))
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
-                            1, 1, 1, 1, 1, 1, 2, 4, 4,
-                            4, 4, 4, 4) {
+                            GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
+                            GROUP(
                MOD_SEL1_31
                MOD_SEL1_30
                MOD_SEL1_29
@@ -2819,7 +2820,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* RESERVED 7, 6, 5, 4  */
                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                /* RESERVED 3, 2, 1, 0  */
-               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
        },
        { },
 };
@@ -2836,6 +2837,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
        return bit;
 }
 
+enum ioctrl_regs {
+       TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [TDSELCTRL] = { 0xe60603c0, },
+       { /* sentinel */ },
+};
+
 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
        .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
 };
@@ -2855,6 +2865,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
        .nr_functions = ARRAY_SIZE(pinmux_functions),
 
        .cfg_regs = pinmux_config_regs,
+       .ioctrl_regs = pinmux_ioctrl_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),