+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
+ */
+
#include <common.h>
#include <dm.h>
-#include <dm/pinctrl.h>
#include <hwspinlock.h>
+#include <log.h>
+#include <malloc.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/libfdt.h>
#define MAX_PINS_ONE_IP 70
#define MODE_BITS_MASK 3
"alt function",
};
+static const char * const pinmux_bias[] = {
+ [STM32_GPIO_PUPD_NO] = "",
+ [STM32_GPIO_PUPD_UP] = "pull-up",
+ [STM32_GPIO_PUPD_DOWN] = "pull-down",
+};
+
+static const char * const pinmux_input[] = {
+ [STM32_GPIO_OTYPE_PP] = "push-pull",
+ [STM32_GPIO_OTYPE_OD] = "open-drain",
+};
+
static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
*/
*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
selector - pin_count);
- if (*idx < 0)
+ if (IS_ERR_VALUE(*idx))
return NULL;
return gpio_bank->gpio_dev;
int size)
{
struct udevice *gpio_dev;
+ struct stm32_gpio_priv *priv;
const char *label;
int mode;
int af_num;
unsigned int gpio_idx;
+ u32 pupd, otype;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
return -ENODEV;
mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
-
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
+ priv = dev_get_priv(gpio_dev);
+ pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
switch (mode) {
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
- snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
+ snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
+ pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
+ snprintf(buf, size, "%s %s %s",
+ pinmux_mode[mode], pinmux_bias[pupd],
+ label ? label : "");
+ break;
case GPIOF_INPUT:
- snprintf(buf, size, "%s %s",
- pinmux_mode[mode], label ? label : "");
+ otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
+ snprintf(buf, size, "%s %s %s %s",
+ pinmux_mode[mode], pinmux_input[otype],
+ pinmux_bias[pupd], label ? label : "");
break;
}
#endif
-int stm32_pinctrl_probe(struct udevice *dev)
+static int stm32_pinctrl_probe(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
int ret;
return 0;
}
-static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
+static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
+ ofnode node)
{
gpio_fn &= 0x00FF;
gpio_ctl->af = 0;
break;
}
- gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
+ gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
- if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
+ if (ofnode_read_bool(node, "drive-open-drain"))
gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
else
gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
- if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
+ if (ofnode_read_bool(node, "bias-pull-up"))
gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
- else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
+ else if (ofnode_read_bool(node, "bias-pull-down"))
gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
else
gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
return 0;
}
-static int stm32_pinctrl_config(int offset)
+static int stm32_pinctrl_config(ofnode node)
{
u32 pin_mux[MAX_PINS_ONE_IP];
int rv, len;
+ ofnode subnode;
/*
* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
* usart1) of pin controller phandle "pinctrl-0"
* */
- fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
+ ofnode_for_each_subnode(subnode, node) {
struct stm32_gpio_dsc gpio_dsc;
struct stm32_gpio_ctl gpio_ctl;
int i;
- len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
- "pinmux", pin_mux,
- ARRAY_SIZE(pin_mux));
+ rv = ofnode_read_size(subnode, "pinmux");
+ if (rv < 0)
+ return rv;
+ len = rv / sizeof(pin_mux[0]);
debug("%s: no of pinmux entries= %d\n", __func__, len);
- if (len < 0)
+ if (len > MAX_PINS_ONE_IP)
return -EINVAL;
+ rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
+ if (rv < 0)
+ return rv;
for (i = 0; i < len; i++) {
struct gpio_desc desc;
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
- prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
+ prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
gpio_dsc.port,
&desc.dev);
return 0;
}
+static int stm32_pinctrl_bind(struct udevice *dev)
+{
+ ofnode node;
+ const char *name;
+ int ret;
+
+ dev_for_each_subnode(node, dev) {
+ debug("%s: bind %s\n", __func__, ofnode_get_name(node));
+
+ ofnode_get_property(node, "gpio-controller", &ret);
+ if (ret < 0)
+ continue;
+ /* Get the name of each gpio node */
+ name = ofnode_get_name(node);
+ if (!name)
+ return -EINVAL;
+
+ /* Bind each gpio node */
+ ret = device_bind_driver_to_node(dev, "gpio_stm32",
+ name, node, NULL);
+ if (ret)
+ return ret;
+
+ debug("%s: bind %s\n", __func__, name);
+ }
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(PINCTRL_FULL)
static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
- return stm32_pinctrl_config(dev_of_offset(config));
+ return stm32_pinctrl_config(dev_ofnode(config));
}
#else /* PINCTRL_FULL */
static int stm32_pinctrl_set_state_simple(struct udevice *dev,
struct udevice *periph)
{
- const void *fdt = gd->fdt_blob;
const fdt32_t *list;
uint32_t phandle;
- int config_node;
+ ofnode config_node;
int size, i, ret;
- list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
+ list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
if (!list)
return -EINVAL;
for (i = 0; i < size; i++) {
phandle = fdt32_to_cpu(*list++);
- config_node = fdt_node_offset_by_phandle(fdt, phandle);
- if (config_node < 0) {
+ config_node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(config_node)) {
pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
return -EINVAL;
}
{ .compatible = "st,stm32f429-pinctrl" },
{ .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
+ { .compatible = "st,stm32f769-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },
.id = UCLASS_PINCTRL,
.of_match = stm32_pinctrl_ids,
.ops = &stm32_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
+ .bind = stm32_pinctrl_bind,
.probe = stm32_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
};