phy: qcom-qmp: move PCS V5 registers to separate headers

[platform/kernel/linux-starfive.git] / drivers / phy / qualcomm / phy-qcom-qmp.h

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 05da072..9d93ae7 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -30,6 +30,11 @@
 #include "phy-qcom-qmp-pcs-usb-v4.h"
 #include "phy-qcom-qmp-pcs-ufs-v4.h"
 
+#include "phy-qcom-qmp-pcs-v5.h"
+#include "phy-qcom-qmp-pcs-pcie-v5.h"
+#include "phy-qcom-qmp-pcs-usb-v5.h"
+#include "phy-qcom-qmp-pcs-ufs-v5.h"
+
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00
 #define QPHY_V3_DP_COM_SW_RESET                                0x04
@@ -334,20 +339,6 @@
 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3  0x218
 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3  0x220
 
-/* Only for QMP V5 PHY - USB/PCIe PCS registers */
-#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1                 0x0dc
-#define QPHY_V5_PCS_G3S2_PRE_GAIN                      0x170
-#define QPHY_V5_PCS_RX_SIGDET_LVL                      0x188
-#define QPHY_V5_PCS_RATE_SLEW_CNTRL1                   0x198
-#define QPHY_V5_PCS_EQ_CONFIG2                         0x1e0
-#define QPHY_V5_PCS_EQ_CONFIG3                         0x1e4
-
-/* Only for QMP V5 PHY - PCS_PCIE registers */
-#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE         0x20
-#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1           0x54
-#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS              0x94
-#define QPHY_V5_PCS_PCIE_EQ_CONFIG2                    0xa8
-
 /* Only for QMP V5_20 PHY - PCIe PCS registers */
 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE      0x01c
 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS           0x090
@@ -356,48 +347,4 @@
 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN                        0x15c
 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3       0x184
 
-/* Only for QMP V5 PHY - UFS PCS registers */
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB   0x00c
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB   0x010
-#define QPHY_V5_PCS_UFS_PLL_CNTL                       0x02c
-#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL           0x030
-#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL           0x038
-#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY           0x074
-#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY           0x0b4
-#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL               0x124
-#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME            0x150
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1                        0x154
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2                        0x158
-#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND               0x160
-#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND                        0x168
-#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1              0x1d8
-#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1               0x1e0
-
-/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
-#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1           0x000
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS                0x004
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL          0x008
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2         0x00c
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR         0x014
-#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL       0x018
-#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART               0x01c
-#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL            0x020
-#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START      0x024
-#define QPHY_V5_PCS_USB3_LFPS_CONFIG1                  0x028
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME                0x02c
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME                0x030
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME                0x034
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2     0x038
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2      0x03c
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L            0x040
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H            0x044
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD          0x048
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY             0x04c
-#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH                0x050
-#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL            0x054
-#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL      0x058
-#define QPHY_V5_PCS_USB3_TEST_CONTROL                  0x05c
-#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL         0x060
-
 #endif