#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
#include <dt-bindings/phy/phy.h>
#define SSUSB_SIFSLV_V1_U3PHYD 0x000
#define SSUSB_SIFSLV_V1_U3PHYA 0x200
+/* version V2 sub-banks offset base address */
+/* u2 phy banks */
+#define SSUSB_SIFSLV_V2_MISC 0x000
+#define SSUSB_SIFSLV_V2_U2FREQ 0x100
+#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
+/* u3/pcie/sata phy banks */
+#define SSUSB_SIFSLV_V2_SPLLC 0x000
+#define SSUSB_SIFSLV_V2_CHIP 0x100
+#define SSUSB_SIFSLV_V2_U3PHYD 0x200
+#define SSUSB_SIFSLV_V2_U3PHYA 0x400
+
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4 0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION2 0x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION9 0x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x) (0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL1 0x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL4 0x58
+#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL6 0x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
+#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
+#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
+
+enum mtk_phy_version {
+ MTK_TPHY_V1 = 1,
+ MTK_TPHY_V2,
+};
+
struct u2phy_banks {
void __iomem *misc;
void __iomem *fmreg;
struct u3phy_banks u3_banks;
};
- /* reference clock of anolog phy */
- struct clk ref_clk;
+ struct clk ref_clk; /* reference clock of (digital) phy */
+ struct clk da_ref_clk; /* reference clock of analog phy */
u32 index;
u32 type;
};
struct mtk_tphy {
struct udevice *dev;
void __iomem *sif_base;
+ enum mtk_phy_version version;
struct mtk_phy_instance **phys;
int nphys;
};
{
struct u3phy_banks *u3_banks = &instance->u3_banks;
+ if (tphy->version != MTK_TPHY_V1)
+ return;
+
clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
udelay(3000);
}
+static void sata_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
+ RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
+ RG_CDR_BIRLTR_GEN1_VAL(0x6) |
+ RG_CDR_BC_GEN1_VAL(0x1a));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
+ RG_CDR_BIRLTD0_GEN1_MSK,
+ RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
+ RG_CDR_BIRLTD0_GEN3_MSK,
+ RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
+ RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
+ RG_CDR_BICLTR_GEN1_VAL(0x0c) |
+ RG_CDR_BR_GEN2_VAL(0x07));
+ clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
+ RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
+ RG_CDR_BICLTD0_GEN1_VAL(0x08) |
+ RG_CDR_BICLTD1_GEN1_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
+ RG_LOCK_CNT_SEL_MSK,
+ RG_LOCK_CNT_SEL_VAL(0x02));
+ clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
+ RG_T2_MIN_MSK | RG_TG_MIN_MSK |
+ RG_T2_MAX_MSK | RG_TG_MAX_MSK,
+ RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
+ RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
+ clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1,
+ RG_IDRV_0DB_GEN1_MSK,
+ RG_IDRV_0DB_GEN1_VAL(0x20));
+ clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1,
+ RG_EQ_DLEQ_LFI_GEN1_MSK,
+ RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
+}
+
static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
break;
+ case PHY_TYPE_SATA:
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
+ break;
+ default:
+ dev_err(tphy->dev, "incompatible PHY type\n");
+ return;
+ }
+}
+
+static void phy_v2_banks_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ switch (instance->type) {
+ case PHY_TYPE_USB2:
+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
+ break;
+ case PHY_TYPE_USB3:
+ case PHY_TYPE_PCIE:
+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
+ break;
default:
dev_err(tphy->dev, "incompatible PHY type\n");
return;
int ret;
ret = clk_enable(&instance->ref_clk);
- if (ret)
+ if (ret < 0) {
+ dev_err(tphy->dev, "failed to enable ref_clk\n");
return ret;
+ }
+
+ ret = clk_enable(&instance->da_ref_clk);
+ if (ret < 0) {
+ dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
+ clk_disable(&instance->ref_clk);
+ return ret;
+ }
switch (instance->type) {
case PHY_TYPE_USB2:
case PHY_TYPE_PCIE:
pcie_phy_instance_init(tphy, instance);
break;
+ case PHY_TYPE_SATA:
+ sata_phy_instance_init(tphy, instance);
+ break;
default:
dev_err(tphy->dev, "incompatible PHY type\n");
return -EINVAL;
struct mtk_tphy *tphy = dev_get_priv(phy->dev);
struct mtk_phy_instance *instance = tphy->phys[phy->id];
+ clk_disable(&instance->da_ref_clk);
clk_disable(&instance->ref_clk);
return 0;
instance->type = args->args[1];
if (!(instance->type == PHY_TYPE_USB2 ||
instance->type == PHY_TYPE_USB3 ||
+ instance->type == PHY_TYPE_SATA ||
instance->type == PHY_TYPE_PCIE)) {
dev_err(phy->dev, "unsupported device type\n");
return -EINVAL;
}
- phy_v1_banks_init(tphy, instance);
+ if (tphy->version == MTK_TPHY_V1) {
+ phy_v1_banks_init(tphy, instance);
+ } else if (tphy->version == MTK_TPHY_V2) {
+ phy_v2_banks_init(tphy, instance);
+ } else {
+ dev_err(phy->dev, "phy version is not supported\n");
+ return -EINVAL;
+ }
return 0;
}
return -ENOMEM;
tphy->dev = dev;
- tphy->sif_base = dev_read_addr_ptr(dev);
- if (!tphy->sif_base)
- return -ENOENT;
+ tphy->version = dev_get_driver_data(dev);
+
+ /* v1 has shared banks for usb/pcie mode, */
+ /* but not for sata mode */
+ if (tphy->version == MTK_TPHY_V1) {
+ tphy->sif_base = dev_read_addr_ptr(dev);
+ }
dev_for_each_subnode(subnode, dev) {
struct mtk_phy_instance *instance;
tphy->phys[index] = instance;
index++;
- err = clk_get_optional_nodev(subnode, "ref",
- &instance->ref_clk);
+ err = clk_get_by_name_nodev_optional(subnode, "ref",
+ &instance->ref_clk);
+ if (err)
+ return err;
+
+ err = clk_get_by_name_nodev_optional(subnode, "da_ref",
+ &instance->da_ref_clk);
if (err)
return err;
}
}
static const struct udevice_id mtk_tphy_id_table[] = {
- { .compatible = "mediatek,generic-tphy-v1", },
+ { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
+ { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
{ }
};
.of_match = mtk_tphy_id_table,
.ops = &mtk_tphy_ops,
.probe = mtk_tphy_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_tphy),
+ .priv_auto = sizeof(struct mtk_tphy),
};
projects / platform / kernel / u-boot.git / blobdiff