{
unsigned long addr;
- if (!res)
- {
+ if (!res) {
DEBUGF("No resource");
goto error;
}
addr = ((res->bus_lower - 1) | (size - 1)) + 1;
- if (addr - res->bus_start + size > res->size)
- {
+ if (addr - res->bus_start + size > res->size) {
DEBUGF("No room in resource");
goto error;
}
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
- {
+ for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
found_mem64 = 0;
/* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE)
- {
+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
- }
- else
- {
+ } else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
}
- if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
- {
+ if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, bar_value);
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
- if (found_mem64)
- {
+ if (found_mem64) {
bar += 4;
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
}
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus + 1);
+ pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
- if (pci_mem)
- {
+ if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
cmdstat |= PCI_COMMAND_MEMORY;
}
- if (pci_io)
- {
+ if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
- if (pci_mem)
- {
+ if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
(pci_mem->bus_lower-1) >> 16);
}
- if (pci_io)
- {
+ if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
hose->pci_io = hose->pci_mem = NULL;
- for (i=0; i<hose->region_count; i++)
- {
- switch(hose->regions[i].flags)
- {
+ for (i=0; i<hose->region_count; i++) {
+ switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
hose->pci_io->size < hose->regions[i].size)
}
- if (hose->pci_mem)
- {
+ if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
hose->pci_mem->bus_start + hose->pci_mem->size - 1);
}
- if (hose->pci_io)
- {
+ if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
unsigned int sub_bus = PCI_BUS(dev);
unsigned short class;
unsigned char prg_iface;
+ int n;
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- switch(class)
- {
+ switch(class) {
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
- pciauto_prescan_setup_bridge(hose, dev, sub_bus);
- pci_hose_scan_bus(hose, hose->current_busno);
+ /* Passing in current_busno allows for sibling P2P bridges */
+ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
+ /*
+ * need to figure out if this is a subordinate bridge on the bus
+ * to be able to properly set the pri/sec/sub bridge registers.
+ */
+ n = pci_hose_scan_bus(hose, hose->current_busno);
+ /* figure out the deepest we've gone for this leg */
+ sub_bus = max(n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
+
sub_bus = hose->current_busno;
break;
case PCI_CLASS_STORAGE_IDE:
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
- if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
- {
- DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
- return sub_bus;
- }
+ if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
+ DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
+ return sub_bus;
+ }
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
break;
/* just do a minimal setup of the bridge, let the OS take care of the rest */
pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
- DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
- PCI_DEV(dev));
+ DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
hose->current_busno++;
break;
+#ifdef CONFIG_MPC5200
+ case PCI_CLASS_BRIDGE_OTHER:
+ DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dev));
+ break;
+#endif
+#ifdef CONFIG_MPC834X
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+ break;
+#endif
default:
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
break;