// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Broadcom
+ * Copyright (C) 2020-2021 Broadcom
*
*/
#include <malloc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/delay.h>
#include <linux/log2.h>
#define EP_PERST_SOURCE_SELECT_SHIFT 2
#define CFG_IND_ADDR_MASK 0x00001ffc
-#define CFG_ADDR_BUS_NUM_SHIFT 20
-#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
-#define CFG_ADDR_DEV_NUM_SHIFT 15
-#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
-#define CFG_ADDR_FUNC_NUM_SHIFT 12
-#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
-#define CFG_ADDR_REG_NUM_SHIFT 2
-#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
-#define CFG_ADDR_CFG_TYPE_SHIFT 0
+#define CFG_ADDR_CFG_ECAM_MASK 0xfffffffc
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
#define IPROC_PCI_PM_CAP 0x48
return -ENODEV;
/* EP device access */
- val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
- (slot << CFG_ADDR_DEV_NUM_SHIFT) |
- (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
- (where & CFG_ADDR_REG_NUM_MASK) |
- (1 & CFG_ADDR_CFG_TYPE_MASK);
+ val = (PCIE_ECAM_OFFSET(busno, slot, fn, where) & CFG_ADDR_CFG_ECAM_MASK)
+ | (1 & CFG_ADDR_CFG_TYPE_MASK);
iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_MEM ||
hose->regions[i].flags == PCI_REGION_PREFETCH) {
- debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
+ debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n",
i, &hose->regions[i].bus_start,
&hose->regions[i].phys_start,
hose->regions[i].size);
while (!pci_get_dma_regions(pcie->dev, ®ions, i)) {
dev_dbg(pcie->dev,
- "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
+ "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n",
i, regions.bus_start, regions.phys_start, regions.size);
/* Each range entry corresponds to an inbound mapping region */
u32 link_status, class;
pcie->link_is_active = false;
- /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
+ /* force class to PCI bridge Normal decode (0x060400) */
#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
-#define PCI_CLASS_BRIDGE_MASK 0xffff00
-#define PCI_CLASS_BRIDGE_SHIFT 8
+#define PCI_BRIDGE_CTRL_REG_CLASS_MASK 0xffffff
iproc_pci_raw_config_read32(pcie, 0,
PCI_BRIDGE_CTRL_REG_OFFSET,
4, &class);
- class &= ~PCI_CLASS_BRIDGE_MASK;
- class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
+ class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK;
+ class |= PCI_CLASS_BRIDGE_PCI_NORMAL;
iproc_pci_raw_config_write32(pcie, 0,
PCI_BRIDGE_CTRL_REG_OFFSET,
4, class);
.ops = &iproc_pcie_ops,
.probe = iproc_pcie_probe,
.remove = iproc_pcie_remove,
- .priv_auto_alloc_size = sizeof(struct iproc_pcie),
- .flags = DM_REMOVE_OS_PREPARE,
+ .priv_auto = sizeof(struct iproc_pcie),
+ .flags = DM_FLAG_OS_PREPARE,
};