#include <common.h>
#include <dm.h>
#include <pci.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
#define RP_TX_REG0 0x2000
#define RP_TX_CNTRL 0x2004
#define IS_ROOT_PORT(pcie, bdf) \
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
-#define PCI_EXP_LNKSTA 18 /* Link Status */
-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
-
/**
* struct intel_fpga_pcie - Intel FPGA PCIe controller state
* @bus: Pointer to the PCI bus
struct intel_fpga_pcie *pcie = dev_get_priv(dev);
pcie->bus = pci_get_controller(dev);
- pcie->first_busno = dev->seq;
+ pcie->first_busno = dev_seq(dev);
/* clear all interrupts */
cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
return 0;
}
-static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
+static int pcie_intel_fpga_of_to_plat(struct udevice *dev)
{
struct intel_fpga_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
.id = UCLASS_PCI,
.of_match = pcie_intel_fpga_ids,
.ops = &pcie_intel_fpga_ops,
- .ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata,
+ .of_to_plat = pcie_intel_fpga_of_to_plat,
.probe = pcie_intel_fpga_probe,
- .priv_auto_alloc_size = sizeof(struct intel_fpga_pcie),
+ .priv_auto = sizeof(struct intel_fpga_pcie),
};