#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "pcie_fsl.h"
if (!pcie->enabled)
return -ENXIO;
- if (PCI_BUS(bdf) < bus->seq)
+ if (PCI_BUS(bdf) < dev_seq(bus))
return -EINVAL;
- if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
+ if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode))
return -EINVAL;
- if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
+ if (PCI_BUS(bdf) == dev_seq(bus) && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
return -EINVAL;
- if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+ if (PCI_BUS(bdf) == (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
return -EINVAL;
return 0;
return 0;
}
- bdf = bdf - PCI_BDF(bus->seq, 0, 0);
- val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+ val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
+ PCI_DEV(bdf), PCI_FUNC(bdf),
+ offset);
out_be32(®s->cfg_addr, val);
sync();
if (fsl_pcie_addr_valid(pcie, bdf))
return 0;
- bdf = bdf - PCI_BDF(bus->seq, 0, 0);
- val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+ val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
+ PCI_DEV(bdf), PCI_FUNC(bdf),
+ offset);
out_be32(®s->cfg_addr, val);
sync();
int ret;
struct udevice *bus = pcie->bus;
- ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
+ ret = fsl_pcie_read_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
offset, valuep, size);
return ret;
{
struct udevice *bus = pcie->bus;
- return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
+ return fsl_pcie_write_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
offset, value, size);
}
if (!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) {
fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
val &= 0xff;
- val |= PCI_CLASS_BRIDGE_PCI << 16;
+ val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
return 0;
}
-static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
+static int fsl_pcie_of_to_plat(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
struct fsl_pcie_data *info;
};
static const struct udevice_id fsl_pcie_ids[] = {
- { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
+ { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
.id = UCLASS_PCI,
.of_match = fsl_pcie_ids,
.ops = &fsl_pcie_ops,
- .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
+ .of_to_plat = fsl_pcie_of_to_plat,
.probe = fsl_pcie_probe,
- .priv_auto_alloc_size = sizeof(struct fsl_pcie),
+ .priv_auto = sizeof(struct fsl_pcie),
};