/* Accessing root port configuration space. */
va_address = (uintptr_t)pcie->ctrl_base;
} else {
+ d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
va_address = (uintptr_t)pcie->cfg_base;
}
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
/* Get the controller base address */
- pcie->ctrl_base = (void *)dev_get_addr_index(dev, 0);
+ pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
return -EINVAL;
/* Get the config space base address and size */
- pcie->cfg_base = (void *)dev_get_addr_size_index(dev, 1,
+ pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
&pcie->cfg_size);
if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
return -EINVAL;