rockchip: rk3128-cru: sync the clock dt-binding header from Linux

[platform/kernel/u-boot.git] / drivers / pci / pci_gt64120.c

diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index a610758..2c2a80e 100644 (file)
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  *
@@ -5,14 +6,12 @@
  *   Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
  *   Authors: Carsten Langgaard <carstenl@mips.com>
  *            Maciej W. Rozycki <macro@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
  */
 
-#include <common.h>
+#include <dm.h>
 #include <gt64120.h>
+#include <init.h>
+#include <log.h>
 #include <pci.h>
 #include <pci_gt64120.h>
 
@@ -49,7 +48,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
 {
        unsigned int bus = PCI_BUS(bdf);
        unsigned int dev = PCI_DEV(bdf);
-       unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
+       unsigned int func = PCI_FUNC(bdf);
        u32 intr;
        u32 addr;
        u32 val;
@@ -66,10 +65,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
        /* Clear cause register bits */
        writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
 
-       addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
-       addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
-       addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
-       addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
+       addr = PCI_CONF1_ADDRESS(bus, dev, func, where);
 
        /* Setup address */
        writel(addr, &gt->regs->pci0_cfgaddr);
@@ -115,64 +111,72 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
        return 0;
 }
 
-static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
-                               int where, u32 *value)
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+                                  uint where, ulong *val,
+                                  enum pci_size_t size)
 {
-       struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
+       struct gt64120_pci_controller *gt = dev_get_priv(dev);
+       u32 data = 0;
 
-       *value = 0xffffffff;
-       return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
-}
+       if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
+               *val = pci_get_ff(size);
+               return 0;
+       }
 
-static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
-                                int where, u32 value)
-{
-       struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-       u32 data = value;
+       *val = pci_conv_32_to_size(data, where, size);
 
-       return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
+       return 0;
 }
 
-void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
-                    unsigned long sys_size, unsigned long mem_bus,
-                    unsigned long mem_phys, unsigned long mem_size,
-                    unsigned long io_bus, unsigned long io_phys,
-                    unsigned long io_size)
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+                                   uint where, ulong val,
+                                   enum pci_size_t size)
 {
-       static struct gt64120_pci_controller global_gt;
-       struct gt64120_pci_controller *gt;
-       struct pci_controller *hose;
+       struct gt64120_pci_controller *gt = dev_get_priv(dev);
+       u32 data = 0;
 
-       gt = &global_gt;
-       gt->regs = regs;
-
-       hose = &gt->hose;
+       if (size == PCI_SIZE_32) {
+               data = val;
+       } else {
+               u32 old;
 
-       hose->first_busno = 0;
-       hose->last_busno = 0;
+               if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
+                       return 0;
 
-       /* System memory space */
-       pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
-                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+               data = pci_conv_size_to_32(old, val, where, size);
+       }
 
-       /* PCI memory space */
-       pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
-                      PCI_REGION_MEM);
+       gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
 
-       /* PCI I/O space */
-       pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
-                      PCI_REGION_IO);
+       return 0;
+}
 
-       hose->region_count = 3;
+static int gt64120_pci_probe(struct udevice *dev)
+{
+       struct gt64120_pci_controller *gt = dev_get_priv(dev);
 
-       pci_set_ops(hose,
-                   pci_hose_read_config_byte_via_dword,
-                   pci_hose_read_config_word_via_dword,
-                   gt_read_config_dword,
-                   pci_hose_write_config_byte_via_dword,
-                   pci_hose_write_config_word_via_dword,
-                   gt_write_config_dword);
+       gt->regs = dev_remap_addr(dev);
+       if (!gt->regs)
+               return -EINVAL;
 
-       pci_register_hose(hose);
-       hose->last_busno = pci_hose_scan(hose);
+       return 0;
 }
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+       .read_config    = gt64120_pci_read_config,
+       .write_config   = gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+       { .compatible = "marvell,pci-gt64120" },
+       { }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+       .name           = "gt64120_pci",
+       .id             = UCLASS_PCI,
+       .of_match       = gt64120_pci_ids,
+       .ops            = &gt64120_pci_ops,
+       .probe          = gt64120_pci_probe,
+       .priv_auto      = sizeof(struct gt64120_pci_controller),
+};