Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1e77884..bb2813f 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -18,8 +18,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_FSL_PCI_INIT
-
 /*
  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  *
@@ -59,8 +57,8 @@ fsl_pci_init(struct pci_controller *hose)
        pci_dev_t dev = PCI_BDF(busno,0,0);
 
        /* Initialize ATMU registers based on hose regions and flags */
-       volatile pot_t *po=&pci->pot[1];        /* skip 0 */
-       volatile pit_t *pi=&pci->pit[0];        /* ranges from: 3 to 1 */
+       volatile pot_t *po = &pci->pot[1];      /* skip 0 */
+       volatile pit_t *pi = &pci->pit[0];      /* ranges from: 3 to 1 */
 
 #ifdef DEBUG
        int neg_link_w;
@@ -112,6 +110,29 @@ fsl_pci_init(struct pci_controller *hose)
                pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
                enabled = ltssm >= PCI_LTSSM_L0;
 
+#ifdef CONFIG_FSL_PCIE_RESET
+               if (ltssm == 1) {
+                       int i;
+                       debug("....PCIe link error. "
+                             "LTSSM=0x%02x.", ltssm);
+                       pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
+                       temp32 = pci->pdb_stat;
+                       udelay(100);
+                       debug("  Asserting PCIe reset @%x = %x\n",
+                             &pci->pdb_stat, pci->pdb_stat);
+                       pci->pdb_stat &= ~0x08000000; /* clear reset */
+                       asm("sync;isync");
+                       for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
+                               pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+                                                       &ltssm);
+                               udelay(1000);
+                               debug("....PCIe link error. "
+                                     "LTSSM=0x%02x.\n", ltssm);
+                       }
+                       enabled = ltssm >= PCI_LTSSM_L0;
+               }
+#endif
+
                if (!enabled) {
                        debug("....PCIE link error.  Skipping scan."
                              "LTSSM=0x%02x\n", ltssm);
@@ -159,7 +180,8 @@ fsl_pci_init(struct pci_controller *hose)
 
        /* Clear all error indications */
 
-       pci->pme_msg_det = 0xffffffff;
+       if (bridge)
+               pci->pme_msg_det = 0xffffffff;
        pci->pedr = 0xffffffff;
 
        pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
@@ -173,5 +195,3 @@ fsl_pci_init(struct pci_controller *hose)
                pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
        }
 }
-
-#endif /* CONFIG_FSL_PCI */