Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 48ae163..621c899 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
        return 1;
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 static void fsl_pcie_boot_master(pit_t *pi)
 {
        /* configure inbound window for slave's u-boot image */
@@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
        /* see if we are a PCIe or PCI controller */
        pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        /* boot from PCIE --master */
        char *s = getenv("bootmaster");
        char pcie[6];
@@ -470,6 +470,28 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                }
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+               if (enabled == 0) {
+                       serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+                       temp32 = in_be32(&srds_regs->srdspccr0);
+
+                       if ((temp32 >> 28) == 3) {
+                               int i;
+
+                               out_be32(&srds_regs->srdspccr0, 2 << 28);
+                               setbits_be32(&pci->pdb_stat, 0x08000000);
+                               in_be32(&pci->pdb_stat);
+                               udelay(100);
+                               clrbits_be32(&pci->pdb_stat, 0x08000000);
+                               asm("sync;isync");
+                               for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+                                       pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
+                                       udelay(1000);
+                               }
+                               enabled = ltssm >= PCI_LTSSM_L0;
+                       }
+               }
+#endif
                if (!enabled) {
                        /* Let the user know there's no PCIe link */
                        printf("no link, regs @ 0x%lx\n", pci_info->regs);
@@ -602,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
        if (fsl_is_pci_agent(hose)) {
                fsl_pci_config_unlock(hose);
                hose->last_busno = hose->first_busno;
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        } else {
                /* boot from PCIE --master releases slave's core 0 */
                char *s = getenv("bootmaster");