Merge tag 'v5.15.57' into rpi-5.15.y

[platform/kernel/linux-rpi.git] / drivers / pci / controller / pcie-brcmstb.c

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index cc30215..44f0ea6 100644 (file)
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -116,8 +116,9 @@
                PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
 
 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG                                 0x4204
-#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK       0x2
-#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK               0x08000000
+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK       BIT(1)
+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK                BIT(21)
+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK               BIT(27)
 
 
 #define PCIE_INTR2_CPU_BASE            0x4300
@@ -283,6 +284,7 @@ struct brcm_pcie {
        struct clk              *clk;
        struct device_node      *np;
        bool                    ssc;
+       bool                    l1ss;
        int                     gen;
        u64                     msi_target_addr;
        struct brcm_msi         *msi;
@@ -469,7 +471,8 @@ static struct irq_chip brcm_msi_irq_chip = {
 
 static struct msi_domain_info brcm_msi_domain_info = {
        /* Multi MSI is supported by the controller, but not by this driver */
-       .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
+       .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+                  MSI_FLAG_PCI_MSIX),
        .chip   = &brcm_msi_irq_chip,
 };
 
@@ -877,6 +880,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 
        /* Reset the bridge */
        pcie->bridge_sw_init_set(pcie, 1);
+       pcie->perst_set(pcie, 1);
+
        usleep_range(100, 200);
 
        /* Take the bridge out of reset */
@@ -1033,12 +1038,25 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
                PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
        writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
 
-       /*
-        * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-        * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
-        */
        tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
-       tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+       if (pcie->l1ss) {
+               /*
+                * Enable CLKREQ# signalling include L1 Substate control of
+                * the CLKREQ# signal and the external reference clock buffer.
+                * meet requirement for Endpoints that require CLKREQ#
+                * assertion to clock active within 400ns.
+                */
+               tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+               tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
+       } else {
+               /*
+                * Refclk from RC should be gated with CLKREQ# input when
+                * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
+                * field to 1.
+                */
+               tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
+               tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+       }
        writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
 
        return 0;
@@ -1267,6 +1285,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
        pcie->gen = (ret < 0) ? 0 : ret;
 
        pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
+       pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
 
        ret = clk_prepare_enable(pcie->clk);
        if (ret) {