Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot...

[platform/kernel/u-boot.git] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3bd0093..a7a6ce9 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -26,8 +26,6 @@
 #include <asm/arch/sys_proto.h>
 #include <linux/errno.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /* Bit/mask specification */
 #define ZYNQ_GEM_PHYMNTNC_OP_MASK      0x40020000 /* operation mask bits */
 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK    0x20000000 /* read operation */
@@ -261,45 +259,6 @@ static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
                            ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 }
 
-static int phy_detection(struct udevice *dev)
-{
-       int i;
-       u16 phyreg = 0;
-       struct zynq_gem_priv *priv = dev->priv;
-
-       if (priv->phyaddr != -1) {
-               phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
-               if ((phyreg != 0xFFFF) &&
-                   ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-                       /* Found a valid PHY address */
-                       debug("Default phy address %d is valid\n",
-                             priv->phyaddr);
-                       return 0;
-               } else {
-                       debug("PHY address is not setup correctly %d\n",
-                             priv->phyaddr);
-                       priv->phyaddr = -1;
-               }
-       }
-
-       debug("detecting phy address\n");
-       if (priv->phyaddr == -1) {
-               /* detect the PHY address */
-               for (i = 31; i >= 0; i--) {
-                       phyread(priv, i, PHY_DETECT_REG, &phyreg);
-                       if ((phyreg != 0xFFFF) &&
-                           ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
-                               /* Found a valid PHY address */
-                               priv->phyaddr = i;
-                               debug("Found valid phy address, %d\n", i);
-                               return 0;
-                       }
-               }
-       }
-       printf("PHY is not detected\n");
-       return -1;
-}
-
 static int zynq_gem_setup_mac(struct udevice *dev)
 {
        u32 i, macaddrlow, macaddrhigh;
@@ -345,28 +304,20 @@ static int zynq_phy_init(struct udevice *dev)
        /* Enable only MDIO bus */
        writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-       if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
-           (priv->interface != PHY_INTERFACE_MODE_GMII)) {
-               ret = phy_detection(dev);
-               if (ret) {
-                       printf("GEM PHY init failed\n");
-                       return ret;
-               }
-       }
-
        priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
                                   priv->interface);
        if (!priv->phydev)
                return -ENODEV;
 
-       priv->phydev->supported &= supported | ADVERTISED_Pause |
-                                 ADVERTISED_Asym_Pause;
        if (priv->max_speed) {
                ret = phy_set_supported(priv->phydev, priv->max_speed);
                if (ret)
                        return ret;
        }
 
+       priv->phydev->supported &= supported | ADVERTISED_Pause |
+                                 ADVERTISED_Asym_Pause;
+
        priv->phydev->advertising = priv->phydev->supported;
        priv->phydev->node = priv->phy_of_node;
 
@@ -512,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
                break;
        }
 
-#if !defined(CONFIG_ARCH_VERSAL)
        ret = clk_set_rate(&priv->clk, clk_rate);
        if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
                dev_err(dev, "failed to set tx clock rate\n");
@@ -524,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
                dev_err(dev, "failed to enable tx clock\n");
                return ret;
        }
-#else
-       debug("requested clk_rate %ld\n", clk_rate);
-#endif
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -800,6 +747,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 }
 
 static const struct udevice_id zynq_gem_ids[] = {
+       { .compatible = "cdns,versal-gem" },
        { .compatible = "cdns,zynqmp-gem" },
        { .compatible = "cdns,zynq-gem" },
        { .compatible = "cdns,gem" },