* SPDX-License-Identifier: GPL-2.0+
*/
+#include <clk.h>
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
-#include <fdtdec.h>
-#include <libfdt.h>
+#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
+#include <wait_bit.h>
#include <watchdog.h>
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
-#if !defined(CONFIG_PHYLIB)
-# error XILINX_GEM_ETHERNET requires PHYLIB
-#endif
+DECLARE_GLOBAL_DATA_PTR;
/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
-#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
-#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
-#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
-#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
+#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
+#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
+#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
+#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
+#ifdef CONFIG_ARM64
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
+#else
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
+#endif
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
+#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
u32 reserved6[18];
#define STAT_SIZE 44
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
- u32 reserved7[164];
+ u32 reserved9[20];
+ u32 pcscntrl;
+ u32 reserved7[143];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
u32 rxbd_current;
u32 rx_first_buf;
int phyaddr;
- u32 emio;
int init;
+ struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
+ int phy_of_handle;
struct mii_dev *bus;
+ struct clk clk;
};
-static inline int mdio_wait(struct eth_device *dev)
-{
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
- u32 timeout = 20000;
-
- /* Wait till MDIO interface is ready to accept a new transaction. */
- while (--timeout) {
- if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
- break;
- WATCHDOG_RESET();
- }
-
- if (!timeout) {
- printf("%s: Timeout\n", __func__);
- return 1;
- }
-
- return 0;
-}
-
-static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
- u32 op, u16 *data)
+static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
+ u32 op, u16 *data)
{
u32 mgtcr;
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+ struct zynq_gem_regs *regs = priv->iobase;
+ int err;
- if (mdio_wait(dev))
- return 1;
+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, true);
+ if (err)
+ return err;
/* Construct mgtcr mask for the operation */
mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
/* Write mgtcr and wait for completion */
writel(mgtcr, ®s->phymntnc);
- if (mdio_wait(dev))
- return 1;
+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, true);
+ if (err)
+ return err;
if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
*data = readl(®s->phymntnc);
return 0;
}
-static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
+static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
+ u32 regnum, u16 *val)
{
u32 ret;
- ret = phy_setup_op(dev, phy_addr, regnum,
- ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
+ ret = phy_setup_op(priv, phy_addr, regnum,
+ ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
if (!ret)
debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
return ret;
}
-static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
+static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
+ u32 regnum, u16 data)
{
debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
regnum, data);
- return phy_setup_op(dev, phy_addr, regnum,
- ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
+ return phy_setup_op(priv, phy_addr, regnum,
+ ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}
-static void phy_detection(struct eth_device *dev)
+static int phy_detection(struct udevice *dev)
{
int i;
u16 phyreg;
struct zynq_gem_priv *priv = dev->priv;
if (priv->phyaddr != -1) {
- phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
+ phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
debug("Default phy address %d is valid\n",
priv->phyaddr);
- return;
+ return 0;
} else {
debug("PHY address is not setup correctly %d\n",
priv->phyaddr);
if (priv->phyaddr == -1) {
/* detect the PHY address */
for (i = 31; i >= 0; i--) {
- phyread(dev, i, PHY_DETECT_REG, &phyreg);
+ phyread(priv, i, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
priv->phyaddr = i;
debug("Found valid phy address, %d\n", i);
- return;
+ return 0;
}
}
}
printf("PHY is not detected\n");
+ return -1;
}
-static int zynq_gem_setup_mac(struct eth_device *dev)
+static int zynq_gem_setup_mac(struct udevice *dev)
{
u32 i, macaddrlow, macaddrhigh;
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct zynq_gem_regs *regs = priv->iobase;
/* Set the MAC bits [31:0] in BOT */
- macaddrlow = dev->enetaddr[0];
- macaddrlow |= dev->enetaddr[1] << 8;
- macaddrlow |= dev->enetaddr[2] << 16;
- macaddrlow |= dev->enetaddr[3] << 24;
+ macaddrlow = pdata->enetaddr[0];
+ macaddrlow |= pdata->enetaddr[1] << 8;
+ macaddrlow |= pdata->enetaddr[2] << 16;
+ macaddrlow |= pdata->enetaddr[3] << 24;
/* Set MAC bits [47:32] in TOP */
- macaddrhigh = dev->enetaddr[4];
- macaddrhigh |= dev->enetaddr[5] << 8;
+ macaddrhigh = pdata->enetaddr[4];
+ macaddrhigh |= pdata->enetaddr[5] << 8;
for (i = 0; i < 4; i++) {
writel(0, ®s->laddr[i][LADDR_LOW]);
return 0;
}
-static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
+static int zynq_phy_init(struct udevice *dev)
{
- u32 i;
- unsigned long clk_rate = 0;
- struct phy_device *phydev;
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
- struct zynq_gem_priv *priv = dev->priv;
- struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
- struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
+ int ret;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct zynq_gem_regs *regs = priv->iobase;
const u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
+ /* Enable only MDIO bus */
+ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
+
+ if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+ ret = phy_detection(dev);
+ if (ret) {
+ printf("GEM PHY init failed\n");
+ return ret;
+ }
+ }
+
+ priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
+ priv->interface);
+ if (!priv->phydev)
+ return -ENODEV;
+
+ priv->phydev->supported = supported | ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause;
+ priv->phydev->advertising = priv->phydev->supported;
+
+ if (priv->phy_of_handle > 0)
+ dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
+
+ return phy_config(priv->phydev);
+}
+
+static int zynq_gem_init(struct udevice *dev)
+{
+ u32 i, nwconfig;
+ int ret;
+ unsigned long clk_rate = 0;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct zynq_gem_regs *regs = priv->iobase;
+ struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
+ struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
+
if (!priv->init) {
/* Disable all interrupts */
writel(0xFFFFFFFF, ®s->idr);
priv->init++;
}
- phy_detection(dev);
+ ret = phy_startup(priv->phydev);
+ if (ret)
+ return ret;
- /* interface - look at tsec */
- phydev = phy_connect(priv->bus, priv->phyaddr, dev,
- priv->interface);
+ if (!priv->phydev->link) {
+ printf("%s: No link.\n", priv->phydev->dev->name);
+ return -1;
+ }
- phydev->supported = supported | ADVERTISED_Pause |
- ADVERTISED_Asym_Pause;
- phydev->advertising = phydev->supported;
- priv->phydev = phydev;
- phy_config(phydev);
- phy_startup(phydev);
+ nwconfig = ZYNQ_GEM_NWCFG_INIT;
- if (!phydev->link) {
- printf("%s: No link.\n", phydev->dev->name);
- return -1;
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+ nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
+ ZYNQ_GEM_NWCFG_PCS_SEL;
+#ifdef CONFIG_ARM64
+ writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ ®s->pcscntrl);
+#endif
}
- switch (phydev->speed) {
+ switch (priv->phydev->speed) {
case SPEED_1000:
- writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
+ writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
®s->nwcfg);
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
- writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
+ writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
®s->nwcfg);
clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
break;
}
- /* Change the rclk and clk only not using EMIO interface */
- if (!priv->emio)
- zynq_slcr_gem_clk_setup(dev->iobase !=
- ZYNQ_GEM_BASEADDR0, clk_rate);
+ ret = clk_set_rate(&priv->clk, clk_rate);
+ if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+ dev_err(dev, "failed to set tx clock rate\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable tx clock\n");
+ return ret;
+ }
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
return 0;
}
-static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
- bool set, unsigned int timeout)
-{
- u32 val;
- unsigned long start = get_timer(0);
-
- while (1) {
- val = readl(reg);
-
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- if (get_timer(start) > timeout)
- break;
-
- udelay(1);
- }
-
- debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- func, reg, mask, set);
-
- return -ETIMEDOUT;
-}
-
-static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
+static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
{
u32 addr, size;
- struct zynq_gem_priv *priv = dev->priv;
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct zynq_gem_regs *regs = priv->iobase;
struct emac_bd *current_bd = &priv->tx_bd[1];
/* Setup Tx BD */
printf("TX buffers exhausted in mid frame\n");
return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
- true, 20000);
+ true, 20000, true);
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
-static int zynq_gem_recv(struct eth_device *dev)
+static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
{
int frame_len;
- struct zynq_gem_priv *priv = dev->priv;
+ u32 addr;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
- struct emac_bd *first_bd;
if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
- return 0;
+ return -1;
if (!(current_bd->status &
(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
printf("GEM: SOF or EOF not set for last buffer received!\n");
- return 0;
+ return -1;
}
frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
- if (frame_len) {
- u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
- addr &= ~(ARCH_DMA_MINALIGN - 1);
+ if (!frame_len) {
+ printf("%s: Zero size packet?\n", __func__);
+ return -1;
+ }
- net_process_received_packet((u8 *)(ulong)addr, frame_len);
+ addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ *packetp = (uchar *)(uintptr_t)addr;
- if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
- priv->rx_first_buf = priv->rxbd_current;
- else {
- current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
- current_bd->status = 0xF0000000; /* FIXME */
- }
+ return frame_len;
+}
- if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
- first_bd = &priv->rx_bd[priv->rx_first_buf];
- first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
- first_bd->status = 0xF0000000;
- }
+static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
+ struct emac_bd *first_bd;
- if ((++priv->rxbd_current) >= RX_BUF)
- priv->rxbd_current = 0;
+ if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
+ priv->rx_first_buf = priv->rxbd_current;
+ } else {
+ current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+ current_bd->status = 0xF0000000; /* FIXME */
}
- return frame_len;
+ if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
+ first_bd = &priv->rx_bd[priv->rx_first_buf];
+ first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+ first_bd->status = 0xF0000000;
+ }
+
+ if ((++priv->rxbd_current) >= RX_BUF)
+ priv->rxbd_current = 0;
+
+ return 0;
}
-static void zynq_gem_halt(struct eth_device *dev)
+static void zynq_gem_halt(struct udevice *dev)
{
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct zynq_gem_regs *regs = priv->iobase;
clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
}
-static int zynq_gem_miiphyread(const char *devname, uchar addr,
- uchar reg, ushort *val)
+__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
- struct eth_device *dev = eth_get_dev();
- int ret;
+ return -ENOSYS;
+}
- ret = phyread(dev, addr, reg, val);
- debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
- return ret;
+static int zynq_gem_read_rom_mac(struct udevice *dev)
+{
+ int retval;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
+ if (retval == -ENOSYS)
+ retval = 0;
+
+ return retval;
}
-static int zynq_gem_miiphy_write(const char *devname, uchar addr,
- uchar reg, ushort val)
+static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
+ int devad, int reg)
{
- struct eth_device *dev = eth_get_dev();
+ struct zynq_gem_priv *priv = bus->priv;
+ int ret;
+ u16 val;
- debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
- return phywrite(dev, addr, reg, val);
+ ret = phyread(priv, addr, reg, &val);
+ debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
+ return val;
}
-int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
- int phy_addr, u32 emio)
+static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
{
- struct eth_device *dev;
- struct zynq_gem_priv *priv;
- void *bd_space;
+ struct zynq_gem_priv *priv = bus->priv;
- dev = calloc(1, sizeof(*dev));
- if (dev == NULL)
- return -1;
+ debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
+ return phywrite(priv, addr, reg, value);
+}
- dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
- if (dev->priv == NULL) {
- free(dev);
- return -1;
- }
- priv = dev->priv;
+static int zynq_gem_probe(struct udevice *dev)
+{
+ void *bd_space;
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ int ret;
/* Align rxbuffers to ARCH_DMA_MINALIGN */
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
- priv->phyaddr = phy_addr;
- priv->emio = emio;
-
-#ifndef CONFIG_ZYNQ_GEM_INTERFACE
- priv->interface = PHY_INTERFACE_MODE_MII;
-#else
- priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
-#endif
+ ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return -EINVAL;
+ }
- sprintf(dev->name, "Gem.%lx", base_addr);
+ priv->bus = mdio_alloc();
+ priv->bus->read = zynq_gem_miiphy_read;
+ priv->bus->write = zynq_gem_miiphy_write;
+ priv->bus->priv = priv;
- dev->iobase = base_addr;
+ ret = mdio_register_seq(priv->bus, dev->seq);
+ if (ret)
+ return ret;
- dev->init = zynq_gem_init;
- dev->halt = zynq_gem_halt;
- dev->send = zynq_gem_send;
- dev->recv = zynq_gem_recv;
- dev->write_hwaddr = zynq_gem_setup_mac;
+ return zynq_phy_init(dev);
+}
- eth_register(dev);
+static int zynq_gem_remove(struct udevice *dev)
+{
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
- miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
- priv->bus = miiphy_get_dev_by_name(dev->name);
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
- return 1;
+ return 0;
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int zynq_gem_of_init(const void *blob)
+static const struct eth_ops zynq_gem_ops = {
+ .start = zynq_gem_init,
+ .send = zynq_gem_send,
+ .recv = zynq_gem_recv,
+ .free_pkt = zynq_gem_free_pkt,
+ .stop = zynq_gem_halt,
+ .write_hwaddr = zynq_gem_setup_mac,
+ .read_rom_hwaddr = zynq_gem_read_rom_mac,
+};
+
+static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
- int offset = 0;
- u32 ret = 0;
- u32 reg, phy_reg;
-
- debug("ZYNQ GEM: Initialization\n");
-
- do {
- offset = fdt_node_offset_by_compatible(blob, offset,
- "xlnx,ps7-ethernet-1.00.a");
- if (offset != -1) {
- reg = fdtdec_get_addr(blob, offset, "reg");
- if (reg != FDT_ADDR_T_NONE) {
- offset = fdtdec_lookup_phandle(blob, offset,
- "phy-handle");
- if (offset != -1)
- phy_reg = fdtdec_get_addr(blob, offset,
- "reg");
- else
- phy_reg = 0;
-
- debug("ZYNQ GEM: addr %x, phyaddr %x\n",
- reg, phy_reg);
-
- ret |= zynq_gem_initialize(NULL, reg,
- phy_reg, 0);
-
- } else {
- debug("ZYNQ GEM: Can't get base address\n");
- return -1;
- }
- }
- } while (offset != -1);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
+ const char *phy_mode;
+
+ pdata->iobase = (phys_addr_t)dev_get_addr(dev);
+ priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
+ /* Hardcode for now */
+ priv->phyaddr = -1;
+
+ priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
+ "phy-handle");
+ if (priv->phy_of_handle > 0)
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+ priv->phy_of_handle, "reg", -1);
+
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+ priv->interface = pdata->phy_interface;
- return ret;
+ printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
+ priv->phyaddr, phy_string_for_interface(priv->interface));
+
+ return 0;
}
-#endif
+
+static const struct udevice_id zynq_gem_ids[] = {
+ { .compatible = "cdns,zynqmp-gem" },
+ { .compatible = "cdns,zynq-gem" },
+ { .compatible = "cdns,gem" },
+ { }
+};
+
+U_BOOT_DRIVER(zynq_gem) = {
+ .name = "zynq_gem",
+ .id = UCLASS_ETH,
+ .of_match = zynq_gem_ids,
+ .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
+ .probe = zynq_gem_probe,
+ .remove = zynq_gem_remove,
+ .ops = &zynq_gem_ops,
+ .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
projects / platform / kernel / u-boot.git / blobdiff