ath9k: fix antenna control configuration for AR9550

[profile/ivi/kernel-x86-ivi.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index ac53d90..57002d1 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3412,11 +3412,11 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
        if (!dump_base_hdr) {
                len += snprintf(buf + len, size - len,
                                "%20s :\n", "2GHz modal Header");
-               len += ar9003_dump_modal_eeprom(buf, len, size,
+               len = ar9003_dump_modal_eeprom(buf, len, size,
                                                &eep->modalHeader2G);
                len += snprintf(buf + len, size - len,
                                "%20s :\n", "5GHz modal Header");
-               len += ar9003_dump_modal_eeprom(buf, len, size,
+               len = ar9003_dump_modal_eeprom(buf, len, size,
                                                &eep->modalHeader5G);
                goto out;
        }
@@ -3509,7 +3509,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 
        if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
-       else if (AR_SREV_9462(ah))
+       else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
        else {
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3591,6 +3591,9 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
        if (AR_SREV_9462(ah)) {
                REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
                                AR_SWITCH_TABLE_COM_AR9462_ALL, value);
+       } else if (AR_SREV_9550(ah)) {
+               REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
+                               AR_SWITCH_TABLE_COM_AR9550_ALL, value);
        } else
                REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
                              AR_SWITCH_TABLE_COM_ALL, value);
@@ -3613,6 +3616,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                value = ar9003_switch_com_spdt_get(ah, is2ghz);
                REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
                                AR_SWITCH_TABLE_COM_SPDT_ALL, value);
+               REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
        }
 
        value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
@@ -3809,7 +3813,7 @@ static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
        return true;
 }
 
-static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
+void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
 {
        int internal_regulator =
                ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);