Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[profile/ivi/kernel-x86-ivi.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index fb892e5..1e22035 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -652,7 +652,7 @@ static const struct ar9300_eeprom ar9300_x113 = {
                .regDmn = { LE16(0), LE16(0x1f) },
                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
                .opCapFlags = {
-                       .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                       .opFlags = AR5416_OPFLAGS_11A,
                        .eepMisc = 0,
                },
                .rfSilent = 0,
@@ -922,7 +922,7 @@ static const struct ar9300_eeprom ar9300_x113 = {
                .db_stage2 = {3, 3, 3}, /* 3 chain */
                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
-               .xpaBiasLvl = 0,
+               .xpaBiasLvl = 0xf,
                .txFrameToDataStart = 0x0e,
                .txFrameToPaOn = 0x0e,
                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
@@ -3442,17 +3442,15 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
 
-       if (AR_SREV_9485(ah))
+       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
        else {
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
-               if (!AR_SREV_9340(ah)) {
-                       REG_RMW_FIELD(ah, AR_CH0_THERM,
-                                     AR_CH0_THERM_XPABIASLVL_MSB,
-                                     bias >> 2);
-                       REG_RMW_FIELD(ah, AR_CH0_THERM,
-                                     AR_CH0_THERM_XPASHORT2GND, 1);
-               }
+               REG_RMW_FIELD(ah, AR_CH0_THERM,
+                               AR_CH0_THERM_XPABIASLVL_MSB,
+                               bias >> 2);
+               REG_RMW_FIELD(ah, AR_CH0_THERM,
+                               AR_CH0_THERM_XPASHORT2GND, 1);
        }
 }
 
@@ -3500,6 +3498,8 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 {
        int chain;
+       u32 regval;
+       u32 ant_div_ctl1;
        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
                        AR_PHY_SWITCH_CHAIN_0,
                        AR_PHY_SWITCH_CHAIN_1,
@@ -3525,13 +3525,49 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 
        if (AR_SREV_9485(ah)) {
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
-               REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
-                             value);
-               REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
-                             value >> 6);
-               REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
-                             value >> 7);
+               /*
+                * main_lnaconf, alt_lnaconf, main_tb, alt_tb
+                * are the fields present
+                */
+               regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+               regval &= (~AR_ANT_DIV_CTRL_ALL);
+               regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
+               /* enable_lnadiv */
+               regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
+               regval |= ((value >> 6) & 0x1) <<
+                               AR_PHY_9485_ANT_DIV_LNADIV_S;
+               REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+
+               /*enable fast_div */
+               regval = REG_READ(ah, AR_PHY_CCK_DETECT);
+               regval &= (~AR_FAST_DIV_ENABLE);
+               regval |= ((value >> 7) & 0x1) <<
+                               AR_FAST_DIV_ENABLE_S;
+               REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
+               ant_div_ctl1 =
+                       ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
+               /* check whether antenna diversity is enabled */
+               if ((ant_div_ctl1 >> 0x6) == 0x3) {
+                       regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+                       /*
+                        * clear bits 25-30 main_lnaconf, alt_lnaconf,
+                        * main_tb, alt_tb
+                        */
+                       regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                                       AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                                       AR_PHY_9485_ANT_DIV_ALT_GAINTB |
+                                       AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
+                       /* by default use LNA1 for the main antenna */
+                       regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
+                                       AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
+                       regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
+                                       AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
+                       REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
+               }
+
+
        }
+
 }
 
 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -4005,6 +4041,16 @@ static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
            );
 
+        /* Write the power for duplicated frames - HT40 */
+
+        /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
+       REG_WRITE(ah, 0xa3e0,
+                 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
+                 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
+                 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
+                 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
+           );
+
        /* Write the HT20 power per rate set */
 
        /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */