#include <net.h>
#include <miiphy.h>
#include <linux/io.h>
+#include <linux/delay.h>
#include <linux/types.h>
#include "smc911x.h"
phys_addr_t iobase;
const struct chip_id *chipid;
unsigned char enetaddr[6];
+ bool use_32_bit_io;
};
static const struct chip_id chip_ids[] = {
#define DRIVERNAME "smc911x"
-#if defined (CONFIG_SMC911X_32_BIT) && \
- defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
- CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-#if defined (CONFIG_SMC911X_32_BIT)
static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
{
- return readl(priv->iobase + offset);
-}
+ if (priv->use_32_bit_io)
+ return readl(priv->iobase + offset);
-static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
-{
- writel(val, priv->iobase + offset);
-}
-#elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
-{
return (readw(priv->iobase + offset) & 0xffff) |
(readw(priv->iobase + offset + 2) << 16);
}
+
static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
{
- writew(val & 0xffff, priv->iobase + offset);
- writew(val >> 16, priv->iobase + offset + 2);
+ if (priv->use_32_bit_io) {
+ writel(val, priv->iobase + offset);
+ } else {
+ writew(val & 0xffff, priv->iobase + offset);
+ writew(val >> 16, priv->iobase + offset + 2);
+ }
}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
{
printf(DRIVERNAME ": MAC %pM\n", m);
}
+static bool smc911x_read_mac_address(struct smc911x_priv *priv)
+{
+ u32 addrh, addrl;
+
+ /* address is obtained from optional eeprom */
+ addrh = smc911x_get_mac_csr(priv, ADDRH);
+ addrl = smc911x_get_mac_csr(priv, ADDRL);
+ if (addrl == 0xffffffff && addrh == 0x0000ffff)
+ return false;
+
+ priv->enetaddr[0] = addrl;
+ priv->enetaddr[1] = addrl >> 8;
+ priv->enetaddr[2] = addrl >> 16;
+ priv->enetaddr[3] = addrl >> 24;
+ priv->enetaddr[4] = addrh;
+ priv->enetaddr[5] = addrh >> 8;
+
+ return true;
+}
+
static int smc911x_eth_phy_read(struct smc911x_priv *priv,
u8 phy, u8 reg, u16 *val)
{
if (!mdiodev)
return -ENOMEM;
- strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+ strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
}
#endif
-static int smc911x_init(struct eth_device *dev, bd_t *bd)
+static int smc911x_init(struct eth_device *dev, struct bd_info *bd)
{
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
return ret;
}
-int smc911x_initialize(u8 dev_num, int base_addr)
+int smc911x_initialize(u8 dev_num, phys_addr_t base_addr)
{
- unsigned long addrl, addrh;
struct smc911x_priv *priv;
int ret;
priv->iobase = base_addr;
priv->dev.iobase = base_addr;
+ priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
/* Try to detect chip. Will fail if not present. */
ret = smc911x_detect_chip(priv);
if (ret) {
goto err_detect;
}
- addrh = smc911x_get_mac_csr(priv, ADDRH);
- addrl = smc911x_get_mac_csr(priv, ADDRL);
- if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
- /* address is obtained from optional eeprom */
- priv->enetaddr[0] = addrl;
- priv->enetaddr[1] = addrl >> 8;
- priv->enetaddr[2] = addrl >> 16;
- priv->enetaddr[3] = addrl >> 24;
- priv->enetaddr[4] = addrh;
- priv->enetaddr[5] = addrh >> 8;
+ if (smc911x_read_mac_address(priv))
memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
- }
priv->dev.init = smc911x_init;
priv->dev.halt = smc911x_halt;
static int smc911x_start(struct udevice *dev)
{
- struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
struct smc911x_priv *priv = dev_get_priv(dev);
memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
return ret ? ret : -EAGAIN;
}
+static int smc911x_read_rom_hwaddr(struct udevice *dev)
+{
+ struct smc911x_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ if (!smc911x_read_mac_address(priv))
+ return -ENODEV;
+
+ memcpy(pdata->enetaddr, priv->enetaddr, sizeof(pdata->enetaddr));
+
+ return 0;
+}
+
static int smc911x_bind(struct udevice *dev)
{
return device_set_name(dev, dev->name);
static int smc911x_probe(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
- unsigned long addrh, addrl;
int ret;
/* Try to detect chip. Will fail if not present. */
if (ret)
return ret;
- addrh = smc911x_get_mac_csr(priv, ADDRH);
- addrl = smc911x_get_mac_csr(priv, ADDRL);
- if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
- /* address is obtained from optional eeprom */
- priv->enetaddr[0] = addrl;
- priv->enetaddr[1] = addrl >> 8;
- priv->enetaddr[2] = addrl >> 16;
- priv->enetaddr[3] = addrl >> 24;
- priv->enetaddr[4] = addrh;
- priv->enetaddr[5] = addrh >> 8;
- }
+ smc911x_read_rom_hwaddr(dev);
return 0;
}
-static int smc911x_ofdata_to_platdata(struct udevice *dev)
+static int smc911x_of_to_plat(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ u32 io_width;
+ int ret;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
+ ret = dev_read_u32(dev, "reg-io-width", &io_width);
+ if (!ret)
+ priv->use_32_bit_io = (io_width == 4);
+ else
+ priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
return 0;
}
.send = smc911x_send,
.recv = smc911x_recv,
.stop = smc911x_stop,
+ .read_rom_hwaddr = smc911x_read_rom_hwaddr,
};
static const struct udevice_id smc911x_ids[] = {
.id = UCLASS_ETH,
.of_match = smc911x_ids,
.bind = smc911x_bind,
- .ofdata_to_platdata = smc911x_ofdata_to_platdata,
+ .of_to_plat = smc911x_of_to_plat,
.probe = smc911x_probe,
.ops = &smc911x_ops,
- .priv_auto_alloc_size = sizeof(struct smc911x_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct smc911x_priv),
+ .plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif