Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi into next

[platform/kernel/u-boot.git] / drivers / net / phy / dp83867.c

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index a43793c..eada454 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -4,13 +4,17 @@
  *
  */
 #include <common.h>
+#include <log.h>
 #include <phy.h>
+#include <dm/devres.h>
+#include <linux/bitops.h>
 #include <linux/compat.h>
 #include <malloc.h>
 
 #include <dm.h>
 #include <dt-bindings/net/ti-dp83867.h>
 
+#include "ti_phy_init.h"
 
 /* TI DP83867 */
 #define DP83867_DEVADDR                0x1f
@@ -28,6 +32,7 @@
 #define DP83867_STRAP_STS2     0x006f
 #define DP83867_RGMIIDCTL      0x0086
 #define DP83867_IO_MUX_CFG     0x0170
+#define DP83867_SGMIICTL       0x00D3
 
 #define DP83867_SW_RESET       BIT(15)
 #define DP83867_SW_RESTART     BIT(14)
@@ -64,6 +69,7 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT         14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK          GENMASK(15, 14)
 #define DP83867_PHYCR_RESERVED_MASK    BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD  BIT(10)
 #define DP83867_MDI_CROSSOVER          5
 #define DP83867_MDI_CROSSOVER_MDIX     2
 #define DP83867_PHYCTRL_SGMIIEN                        0x0800
@@ -99,6 +105,9 @@
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN            BIT(0)
 
+/* SGMIICTL bits */
+#define DP83867_SGMII_TYPE                     BIT(14)
+
 enum {
        DP83867_PORT_MIRRORING_KEEP,
        DP83867_PORT_MIRRORING_EN,
@@ -114,6 +123,7 @@ struct dp83867_private {
        int port_mirroring;
        bool set_clk_output;
        unsigned int clk_output_sel;
+       bool sgmii_ref_clk_en;
 };
 
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
@@ -234,6 +244,9 @@ static int dp83867_of_init(struct phy_device *phydev)
        if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
                dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 
+       if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
+               dp83867->sgmii_ref_clk_en = true;
+
        return 0;
 }
 #else
@@ -283,6 +296,9 @@ static int dp83867_config(struct phy_device *phydev)
                val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
                val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
+               /* Do not force link good */
+               val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
                /* The code below checks if "port mirroring" N/A MODE4 has been
                 * enabled during power on bootstrap.
                 *
@@ -326,6 +342,10 @@ static int dp83867_config(struct phy_device *phydev)
        }
 
        if (phy_interface_is_sgmii(phydev)) {
+               if (dp83867->sgmii_ref_clk_en)
+                       phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
+                                     DP83867_SGMII_TYPE);
+
                phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
                          (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 
@@ -411,7 +431,7 @@ static struct phy_driver DP83867_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-int phy_ti_init(void)
+int phy_dp83867_init(void)
 {
        phy_register(&DP83867_driver);
        return 0;