+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
*
* This driver for AMD PCnet network controllers is derived from the
* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
+#include <log.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
+#include <asm/cache.h>
#include <asm/io.h>
#include <pci.h>
+#include <linux/delay.h>
#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
#define PCNET_DEBUG2(fmt,args...) \
debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
-#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
-#error "Macro for PCnet chip version is not defined!"
-#endif
-
/*
* Set the number of Tx and Rx buffers, using Log_2(# buffers).
* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
struct pcnet_init_block init_block;
};
-typedef struct pcnet_priv {
+struct pcnet_priv {
struct pcnet_uncached_priv *uc;
/* Receive Buffer space */
unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
int cur_rx;
int cur_tx;
-} pcnet_priv_t;
+};
-static pcnet_priv_t *lp;
+static struct pcnet_priv *lp;
/* Offsets from base I/O address for WIO mode */
#define PCNET_RDP 0x10
static u16 pcnet_read_csr(struct eth_device *dev, int index)
{
- outw(index, dev->iobase + PCNET_RAP);
- return inw(dev->iobase + PCNET_RDP);
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ writew(index, base + PCNET_RAP);
+ return readw(base + PCNET_RDP);
}
static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
{
- outw(index, dev->iobase + PCNET_RAP);
- outw(val, dev->iobase + PCNET_RDP);
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ writew(index, base + PCNET_RAP);
+ writew(val, base + PCNET_RDP);
}
static u16 pcnet_read_bcr(struct eth_device *dev, int index)
{
- outw(index, dev->iobase + PCNET_RAP);
- return inw(dev->iobase + PCNET_BDP);
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ writew(index, base + PCNET_RAP);
+ return readw(base + PCNET_BDP);
}
static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
{
- outw(index, dev->iobase + PCNET_RAP);
- outw(val, dev->iobase + PCNET_BDP);
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ writew(index, base + PCNET_RAP);
+ writew(val, base + PCNET_BDP);
}
static void pcnet_reset(struct eth_device *dev)
{
- inw(dev->iobase + PCNET_RESET);
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ readw(base + PCNET_RESET);
}
static int pcnet_check(struct eth_device *dev)
{
- outw(88, dev->iobase + PCNET_RAP);
- return inw(dev->iobase + PCNET_RAP) == 88;
+ void __iomem *base = (void __iomem *)dev->iobase;
+
+ writew(88, base + PCNET_RAP);
+ return readw(base + PCNET_RAP) == 88;
}
static int pcnet_init (struct eth_device *dev, bd_t * bis);
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
+ u32 bar;
PCNET_DEBUG1("\npcnet_initialize...\n");
/*
* Setup the PCI device.
*/
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
- (unsigned int *)&dev->iobase);
- dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
+ dev->iobase = pci_mem_to_phys(devbusfn, bar);
dev->iobase &= ~0xf;
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
dev->name, devbusfn, (unsigned long)dev->iobase);
- command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, command);
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
if ((status & command) != command) {
{
int chip_version;
char *chipname;
-
-#ifdef PCNET_HAS_PROM
int i;
-#endif
/* Reset the PCnet controller */
pcnet_reset(dev);
case 0x2621:
chipname = "PCnet/PCI II 79C970A"; /* PCI */
break;
-#ifdef CONFIG_PCNET_79C973
case 0x2625:
chipname = "PCnet/FAST III 79C973"; /* PCI */
break;
-#endif
-#ifdef CONFIG_PCNET_79C975
case 0x2627:
chipname = "PCnet/FAST III 79C975"; /* PCI */
break;
-#endif
default:
printf("%s: PCnet version %#x not supported\n",
dev->name, chip_version);
PCNET_DEBUG1("AMD %s\n", chipname);
-#ifdef PCNET_HAS_PROM
/*
* In most chips, after a chip reset, the ethernet address is read from
* the station address PROM at the base address and programmed into the
dev->enetaddr[2 * i] = val & 0x0ff;
dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
}
-#endif /* PCNET_HAS_PROM */
return 0;
}
* must be aligned on 16-byte boundaries.
*/
if (lp == NULL) {
- addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
+ addr = (unsigned long)malloc(sizeof(*lp) + 0x10);
addr = (addr + 0xf) & ~0xf;
- lp = (pcnet_priv_t *)addr;
+ lp = (struct pcnet_priv *)addr;
addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
sizeof(*lp->uc));
flush_dcache_range(addr, addr + sizeof(*lp->uc));
- addr = UNCACHED_SDRAM(addr);
+ addr = (unsigned long)map_physmem(addr,
+ roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
+ MAP_NOCACHE);
lp->uc = (struct pcnet_uncached_priv *)addr;
addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
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