#include <common.h>
#include <cpu_func.h>
+#include <dm.h>
#include <log.h>
+#include <dm.h>
#include <malloc.h>
#include <memalign.h>
#include <net.h>
/* Receive Buffer space */
unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
struct pcnet_uncached_priv *uc;
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+ const char *name;
+#else
pci_dev_t dev;
+ char *name;
+#endif
void __iomem *iobase;
+ u8 *enetaddr;
+ u16 status;
int cur_rx;
int cur_tx;
};
{
void *virt_addr = addr;
+#ifdef CONFIG_DM_ETH
+ return dm_pci_virt_to_mem(lp->dev, virt_addr);
+#else
return pci_virt_to_mem(lp->dev, virt_addr);
+#endif
}
static struct pci_device_id supported[] = {
{}
};
-static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
+static int pcnet_probe_common(struct pcnet_priv *lp)
{
- struct pcnet_priv *lp = dev->priv;
int chip_version;
char *chipname;
int i;
/* Check if register access is working */
if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
- printf("%s: CSR register access check failed\n", dev->name);
+ printf("%s: CSR register access check failed\n", lp->name);
return -1;
}
break;
default:
printf("%s: PCnet version %#x not supported\n",
- dev->name, chip_version);
+ lp->name, chip_version);
return -1;
}
val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
/* There may be endianness issues here. */
- dev->enetaddr[2 * i] = val & 0x0ff;
- dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
+ lp->enetaddr[2 * i] = val & 0x0ff;
+ lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
}
return 0;
}
-static int pcnet_init(struct eth_device *dev, bd_t *bis)
+static int pcnet_init_common(struct pcnet_priv *lp)
{
- struct pcnet_priv *lp = dev->priv;
struct pcnet_uncached_priv *uc;
int i, val;
unsigned long addr;
- PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
+ PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
/* Switch pcnet to 32bit mode */
pcnet_write_bcr(lp, 20, 2);
PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
for (i = 0; i < 6; i++) {
- lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
+ lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
}
udelay(10);
}
if (i <= 0) {
- printf("%s: TIMEOUT: controller init failed\n", dev->name);
+ printf("%s: TIMEOUT: controller init failed\n", lp->name);
pcnet_reset(lp);
return -1;
}
return 0;
}
-static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
+static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
{
- struct pcnet_priv *lp = dev->priv;
int i, status;
u32 addr;
struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
}
if (i <= 0) {
printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
- dev->name, lp->cur_tx, status);
+ lp->name, lp->cur_tx, status);
pkt_len = 0;
goto failure;
}
return pkt_len;
}
-static int pcnet_recv (struct eth_device *dev)
+static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
{
- struct pcnet_priv *lp = dev->priv;
struct pcnet_rx_head *entry;
unsigned char *buf;
int pkt_len = 0;
- u16 status, err_status;
-
- while (1) {
- entry = &lp->uc->rx_ring[lp->cur_rx];
- /*
- * If we own the next entry, it's a new packet. Send it up.
- */
- status = readw(&entry->status);
- if ((status & 0x8000) != 0)
- break;
- err_status = status >> 8;
-
- if (err_status != 0x03) { /* There was an error. */
- printf("%s: Rx%d", dev->name, lp->cur_rx);
- PCNET_DEBUG1(" (status=0x%x)", err_status);
- if (err_status & 0x20)
- printf(" Frame");
- if (err_status & 0x10)
- printf(" Overflow");
- if (err_status & 0x08)
- printf(" CRC");
- if (err_status & 0x04)
- printf(" Fifo");
- printf(" Error\n");
- status &= 0x03ff;
-
- } else {
- pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
- if (pkt_len < 60) {
- printf("%s: Rx%d: invalid packet length %d\n",
- dev->name, lp->cur_rx, pkt_len);
- } else {
- buf = lp->rx_buf[lp->cur_rx];
- invalidate_dcache_range((unsigned long)buf,
- (unsigned long)buf + pkt_len);
- net_process_received_packet(buf, pkt_len);
- PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
- lp->cur_rx, pkt_len, buf);
- }
- }
+ u16 err_status;
- status |= 0x8000;
- writew(status, &entry->status);
+ entry = &lp->uc->rx_ring[lp->cur_rx];
+ /*
+ * If we own the next entry, it's a new packet. Send it up.
+ */
+ lp->status = readw(&entry->status);
+ if ((lp->status & 0x8000) != 0)
+ return 0;
+ err_status = lp->status >> 8;
+
+ if (err_status != 0x03) { /* There was an error. */
+ printf("%s: Rx%d", lp->name, lp->cur_rx);
+ PCNET_DEBUG1(" (status=0x%x)", err_status);
+ if (err_status & 0x20)
+ printf(" Frame");
+ if (err_status & 0x10)
+ printf(" Overflow");
+ if (err_status & 0x08)
+ printf(" CRC");
+ if (err_status & 0x04)
+ printf(" Fifo");
+ printf(" Error\n");
+ lp->status &= 0x03ff;
+ return 0;
+ }
- if (++lp->cur_rx >= RX_RING_SIZE)
- lp->cur_rx = 0;
+ pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
+ if (pkt_len < 60) {
+ printf("%s: Rx%d: invalid packet length %d\n",
+ lp->name, lp->cur_rx, pkt_len);
+ return 0;
}
+
+ *bufp = lp->rx_buf[lp->cur_rx];
+ invalidate_dcache_range((unsigned long)*bufp,
+ (unsigned long)*bufp + pkt_len);
+
+ PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
+ lp->cur_rx, pkt_len, buf);
+
return pkt_len;
}
-static void pcnet_halt(struct eth_device *dev)
+static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
+{
+ struct pcnet_rx_head *entry;
+
+ entry = &lp->uc->rx_ring[lp->cur_rx];
+
+ lp->status |= 0x8000;
+ writew(lp->status, &entry->status);
+
+ if (++lp->cur_rx >= RX_RING_SIZE)
+ lp->cur_rx = 0;
+}
+
+static void pcnet_halt_common(struct pcnet_priv *lp)
{
- struct pcnet_priv *lp = dev->priv;
int i;
- PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
+ PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
/* Reset the PCnet controller */
pcnet_reset(lp);
udelay(10);
}
if (i <= 0)
- printf("%s: TIMEOUT: controller reset failed\n", dev->name);
+ printf("%s: TIMEOUT: controller reset failed\n", lp->name);
+}
+
+#ifndef CONFIG_DM_ETH
+static int pcnet_init(struct eth_device *dev, bd_t *bis)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ return pcnet_init_common(lp);
+}
+
+static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ return pcnet_send_common(lp, packet, pkt_len);
+}
+
+static int pcnet_recv(struct eth_device *dev)
+{
+ struct pcnet_priv *lp = dev->priv;
+ uchar *packet;
+ int ret;
+
+ ret = pcnet_recv_common(lp, &packet);
+ if (ret > 0)
+ net_process_received_packet(packet, ret);
+ if (ret)
+ pcnet_free_pkt_common(lp, ret);
+
+ return ret;
+}
+
+static void pcnet_halt(struct eth_device *dev)
+{
+ struct pcnet_priv *lp = dev->priv;
+
+ pcnet_halt_common(lp);
}
int pcnet_initialize(bd_t *bis)
int dev_nr = 0;
u32 bar;
- PCNET_DEBUG1("\npcnet_initialize...\n");
+ PCNET_DEBUG1("\n%s...\n", __func__);
for (dev_nr = 0; ; dev_nr++) {
/*
(unsigned long)lp + sizeof(*lp));
dev->priv = lp;
sprintf(dev->name, "pcnet#%d", dev_nr);
+ lp->name = dev->name;
+ lp->enetaddr = dev->enetaddr;
/*
* Setup the PCI device.
lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
- dev->name, devbusfn, lp->iobase);
+ lp->name, devbusfn, lp->iobase);
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, command);
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
if ((status & command) != command) {
printf("%s: Couldn't enable IO access or Bus Mastering\n",
- dev->name);
+ lp->name);
free(dev);
continue;
}
/*
* Probe the PCnet chip.
*/
- if (pcnet_probe(dev, bis, dev_nr) < 0) {
+ if (pcnet_probe_common(lp) < 0) {
free(dev);
continue;
}
return dev_nr;
}
+#else /* DM_ETH */
+static int pcnet_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+ return pcnet_init_common(priv);
+}
+
+static void pcnet_stop(struct udevice *dev)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ pcnet_halt_common(priv);
+}
+
+static int pcnet_send(struct udevice *dev, void *packet, int length)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = pcnet_send_common(priv, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
+}
+
+static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ return pcnet_recv_common(priv, packetp);
+}
+
+static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct pcnet_priv *priv = dev_get_priv(dev);
+
+ pcnet_free_pkt_common(priv, length);
+
+ return 0;
+}
+
+static int pcnet_bind(struct udevice *dev)
+{
+ static int card_number;
+ char name[16];
+
+ sprintf(name, "pcnet#%u", card_number++);
+
+ return device_set_name(dev, name);
+}
+
+static int pcnet_probe(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct pcnet_priv *lp = dev_get_priv(dev);
+ u16 command, status;
+ u32 iobase;
+ int ret;
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
+ iobase &= ~0xf;
+
+ lp->uc = map_physmem((phys_addr_t)&lp->ucp,
+ sizeof(lp->ucp), MAP_NOCACHE);
+ lp->dev = dev;
+ lp->name = dev->name;
+ lp->enetaddr = plat->enetaddr;
+ lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
+
+ flush_dcache_range((unsigned long)lp,
+ (unsigned long)lp + sizeof(*lp));
+
+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, command);
+ dm_pci_read_config16(dev, PCI_COMMAND, &status);
+ if ((status & command) != command) {
+ printf("%s: Couldn't enable IO access or Bus Mastering\n",
+ lp->name);
+ return -EINVAL;
+ }
+
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
+
+ ret = pcnet_probe_common(lp);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct eth_ops pcnet_ops = {
+ .start = pcnet_start,
+ .send = pcnet_send,
+ .recv = pcnet_recv,
+ .stop = pcnet_stop,
+ .free_pkt = pcnet_free_pkt,
+};
+
+U_BOOT_DRIVER(eth_pcnet) = {
+ .name = "eth_pcnet",
+ .id = UCLASS_ETH,
+ .bind = pcnet_bind,
+ .probe = pcnet_probe,
+ .ops = &pcnet_ops,
+ .priv_auto_alloc_size = sizeof(struct pcnet_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
+};
+
+U_BOOT_PCI_DEVICE(eth_pcnet, supported);
+#endif