#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
+#ifndef CONFIG_DM_ETH
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#endif
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
/* port device data struct */
struct mvgbe_device {
+#ifndef CONFIG_DM_ETH
struct eth_device dev;
+#endif
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
+
+#ifdef CONFIG_DM_ETH
+ phy_interface_t phy_interface;
+ unsigned int link;
+ unsigned int duplex;
+ unsigned int speed;
+
+ int init;
+ int phyaddr;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+#endif
};
#endif /* __MVGBE_H__ */