#include <common.h>
#include <config.h>
#include <dm.h>
+#include <log.h>
+#include <malloc.h>
#include <dm/of_access.h>
#include <dm/of_addr.h>
#include <fdt_support.h>
+#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
-#define MIIM_STATUS 0x0
-#define MIIM_STAT_BUSY BIT(3)
-#define MIIM_CMD 0x8
-#define MIIM_CMD_SCAN BIT(0)
-#define MIIM_CMD_OPR_WRITE BIT(1)
-#define MIIM_CMD_OPR_READ BIT(2)
-#define MIIM_CMD_SINGLE_SCAN BIT(3)
-#define MIIM_CMD_WRDATA(x) ((x) << 4)
-#define MIIM_CMD_REGAD(x) ((x) << 20)
-#define MIIM_CMD_PHYAD(x) ((x) << 25)
-#define MIIM_CMD_VLD BIT(31)
-#define MIIM_DATA 0xC
-#define MIIM_DATA_ERROR (0x2 << 16)
+#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
+#include "mscc_miim.h"
#define PHY_CFG 0x0
#define PHY_CFG_ENA 0xF
#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
-#define ANA_TABLES_MACHDATA 0x8b34
-#define ANA_TABLES_MACLDATA 0x8b38
-#define ANA_TABLES_MACACCESS 0x8b3c
-#define ANA_TABLES_MACACCESS_VALID BIT(11)
-#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
-#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
-#define MACACCESS_CMD_IDLE 0
-#define MACACCESS_CMD_LEARN 1
-#define MACACCESS_CMD_GET_NEXT 4
#define ANA_PGID(x) (0x8c00 + 4 * (x))
+#define HSIO_ANA_SERDES1G_DES_CFG 0x4c
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
+#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_IB_CFG 0x50
+#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
+#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
+#define HSIO_ANA_SERDES1G_OB_CFG 0x54
+#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
+#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
+#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
+#define HSIO_ANA_SERDES1G_SER_CFG 0x58
+#define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c
+#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
+#define HSIO_ANA_SERDES1G_PLL_CFG 0x60
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
+#define HSIO_DIG_SERDES1G_DFT_CFG0 0x68
+#define HSIO_DIG_SERDES1G_MISC_CFG 0x7c
+#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
+#define HSIO_MCB_SERDES1G_CFG 0x88
+#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
+#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
+#define HSIO_HW_CFGSTAT_HW_CFG 0x10c
+
#define SYS_FRM_AGING 0x574
#define SYS_FRM_AGING_ENA BIT(20)
#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
-#define QS_XTR_RD(x) (0x8 + 4 * (x))
-#define QS_XTR_FLUSH 0x18
-#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
-#define QS_XTR_DATA_PRESENT 0x1c
#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
-#define QS_INJ_WR(x) (0x2c + 4 * (x))
-#define QS_INJ_CTRL(x) (0x34 + 4 * (x))
-#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
-#define QS_INJ_CTRL_EOF BIT(19)
-#define QS_INJ_CTRL_SOF BIT(18)
-#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
-
-#define XTR_EOF_0 ntohl(0x80000000u)
-#define XTR_EOF_1 ntohl(0x80000001u)
-#define XTR_EOF_2 ntohl(0x80000002u)
-#define XTR_EOF_3 ntohl(0x80000003u)
-#define XTR_PRUNED ntohl(0x80000004u)
-#define XTR_ABORT ntohl(0x80000005u)
-#define XTR_ESCAPE ntohl(0x80000006u)
-#define XTR_NOT_READY ntohl(0x80000007u)
#define IFH_INJ_BYPASS BIT(31)
-#define IFH_TAG_TYPE_C 0
-#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
-#define MAC_VID 1
+#define IFH_TAG_TYPE_C 0
+#define MAC_VID 1
#define CPU_PORT 11
-#define INTERNAL_PORT_MSK 0xF
+#define INTERNAL_PORT_MSK 0x2FF
#define IFH_LEN 4
-#define OCELOT_BUF_CELL_SZ 60
#define ETH_ALEN 6
-#define PGID_BROADCAST 13
-#define PGID_UNICAST 14
-#define PGID_SRC 80
+#define PGID_BROADCAST 13
+#define PGID_UNICAST 14
+#define PGID_SRC 80
-enum ocelot_target {
- ANA,
- QS,
- QSYS,
- REW,
- SYS,
- HSIO,
- PORT0,
- PORT1,
- PORT2,
- PORT3,
- TARGET_MAX,
+static const char * const regs_names[] = {
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana",
};
-#define MAX_PORT (PORT3 - PORT0)
+#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
+#define MAX_PORT 11
-/* MAC table entry types.
- * ENTRYTYPE_NORMAL is subject to aging.
- * ENTRYTYPE_LOCKED is not subject to aging.
- * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
- * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
- */
-enum macaccess_entry_type {
- ENTRYTYPE_NORMAL = 0,
- ENTRYTYPE_LOCKED,
- ENTRYTYPE_MACv4,
- ENTRYTYPE_MACv6,
+enum ocelot_ctrl_regs {
+ SYS = MAX_PORT,
+ REW,
+ QS,
+ HSIO,
+ QSYS,
+ ANA,
};
-enum ocelot_mdio_target {
- MIIM,
- PHY,
- TARGET_MDIO_MAX,
-};
+#define OCELOT_MIIM_BUS_COUNT 2
-enum ocelot_phy_id {
- INTERNAL,
- EXTERNAL,
- NUM_PHY,
+struct ocelot_phy_port_t {
+ size_t phy_addr;
+ struct mii_dev *bus;
+ u8 serdes_index;
+ u8 phy_mode;
};
struct ocelot_private {
- void __iomem *regs[TARGET_MAX];
-
- struct mii_dev *bus[NUM_PHY];
- struct phy_device *phydev;
- int phy_mode;
- int max_speed;
+ void __iomem *regs[REGS_NAMES_COUNT];
+ struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT];
+ struct ocelot_phy_port_t ports[MAX_PORT];
+};
- int rx_pos;
- int rx_siz;
- int rx_off;
- int tx_num;
+static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
+static int miim_count = -1;
- u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
- void *tx_adj_buf;
+static const unsigned long ocelot_regs_qs[] = {
+ [MSCC_QS_XTR_RD] = 0x8,
+ [MSCC_QS_XTR_FLUSH] = 0x18,
+ [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
+ [MSCC_QS_INJ_WR] = 0x2c,
+ [MSCC_QS_INJ_CTRL] = 0x34,
};
-struct mscc_miim_dev {
- void __iomem *regs;
- void __iomem *phy_regs;
+static const unsigned long ocelot_regs_ana_table[] = {
+ [MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
+ [MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
+ [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
};
-struct mscc_miim_dev miim[NUM_PHY];
-
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+static void mscc_phy_reset(void)
{
- return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
- false, 250, false);
-}
-
-static int mscc_miim_reset(struct mii_dev *bus)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
-
- if (miim->phy_regs) {
- writel(0, miim->phy_regs + PHY_CFG);
- writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
- | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
- mdelay(500);
+ writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
+ if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) +
+ PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
+ true, 2000, false)) {
+ pr_err("Timeout in phy reset\n");
}
-
- return 0;
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
- MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
- miim->regs + MIIM_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + MIIM_DATA);
- if (val & MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
- MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
- MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
- out:
- return ret;
-}
-
-/* For now only setup the internal mdio bus */
-static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
-{
- unsigned long phy_size[TARGET_MAX];
- phys_addr_t phy_base[TARGET_MAX];
- struct ofnode_phandle_args phandle;
- ofnode eth_node, node, mdio_node;
- struct resource res;
- struct mii_dev *bus;
- fdt32_t faddr;
- int i;
-
- bus = mdio_alloc();
-
- if (!bus)
- return NULL;
-
- /* gathered only the first mdio bus */
- eth_node = dev_read_first_subnode(dev);
- node = ofnode_first_subnode(eth_node);
- ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
- &phandle);
- mdio_node = ofnode_get_parent(phandle.node);
-
- for (i = 0; i < TARGET_MDIO_MAX; i++) {
- if (ofnode_read_resource(mdio_node, i, &res)) {
- pr_err("%s: get OF resource failed\n", __func__);
- return NULL;
- }
- faddr = cpu_to_fdt32(res.start);
- phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
- phy_size[i] = res.end - res.start;
- }
-
- strcpy(bus->name, "miim-internal");
- miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
- miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
- bus->priv = &miim[INTERNAL];
- bus->reset = mscc_miim_reset;
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
- else
- return bus;
}
__weak void mscc_switch_reset(void)
static void ocelot_stop(struct udevice *dev)
{
- struct ocelot_private *priv = dev_get_priv(dev);
- int i;
-
mscc_switch_reset();
- for (i = 0; i < NUM_PHY; i++)
- if (priv->bus[i])
- mscc_miim_reset(priv->bus[i]);
+ mscc_phy_reset();
}
static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
/* Make VLAN aware for CPU traffic */
writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
- MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
/* Enable the port in the core */
- setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
QSYS_SWITCH_PORT_MODE_PORT_ENA);
}
+static void serdes1g_write(void __iomem *base, u32 addr)
+{
+ u32 data;
+
+ writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
+ HSIO_MCB_SERDES1G_CFG_ADDR(addr),
+ base + HSIO_MCB_SERDES1G_CFG);
+
+ do {
+ data = readl(base + HSIO_MCB_SERDES1G_CFG);
+ } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
+}
+
+static void serdes1g_setup(void __iomem *base, uint32_t addr,
+ phy_interface_t interface)
+{
+ writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG);
+
+ writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
+ writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
+ writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
+ HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
+ HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
+ base + HSIO_ANA_SERDES1G_IB_CFG);
+ writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
+ HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
+ HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
+ HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
+ base + HSIO_ANA_SERDES1G_DES_CFG);
+ writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
+ HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
+ HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
+ HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
+ HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
+ base + HSIO_ANA_SERDES1G_OB_CFG);
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
+ HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
+ HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
+ base + HSIO_ANA_SERDES1G_PLL_CFG);
+ writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
+ base + HSIO_DIG_SERDES1G_MISC_CFG);
+
+ serdes1g_write(base, addr);
+
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ serdes1g_write(base, addr);
+
+ writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
+ serdes1g_write(base, addr);
+}
+
+static void serdes_setup(struct ocelot_private *priv)
+{
+ size_t mask;
+ int i = 0;
+
+ for (i = 0; i < MAX_PORT; ++i) {
+ if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
+ continue;
+
+ mask = BIT(priv->ports[i].serdes_index);
+ serdes1g_setup(priv->regs[HSIO], mask,
+ priv->ports[i].phy_mode);
+ }
+}
+
static int ocelot_switch_init(struct ocelot_private *priv)
{
/* Reset switch & memories */
setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
SYS_SYSTEM_RST_CORE_ENA);
+ serdes_setup(priv);
return 0;
}
-static void ocelot_switch_flush(struct ocelot_private *priv)
-{
- /* All Queues flush */
- setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
- /* Allow to drain */
- mdelay(1);
- /* All Queues normal */
- clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
-}
-
static int ocelot_initialize(struct ocelot_private *priv)
{
int ret, i;
* Put fron ports in "port isolation modes" - i.e. they cant send
* to other ports - via the PGID sorce masks.
*/
- for (i = 0; i <= MAX_PORT; i++)
+ for (i = 0; i < MAX_PORT; i++)
writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
/* Flush queues */
- ocelot_switch_flush(priv);
+ mscc_flush(priv->regs[QS], ocelot_regs_qs);
/* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
writel(SYS_FRM_AGING_ENA | (20000000 / 65),
priv->regs[SYS] + SYS_FRM_AGING);
- for (i = PORT0; i <= PORT3; i++)
+ for (i = 0; i < MAX_PORT; i++)
ocelot_port_init(priv, i);
ocelot_cpu_capture_setup(priv);
return 0;
}
-static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
-{
- unsigned int val, timeout = 10;
-
- /* Wait for the issued mac table command to be completed, or timeout.
- * When the command read from ANA_TABLES_MACACCESS is
- * MACACCESS_CMD_IDLE, the issued command completed successfully.
- */
- do {
- val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
- val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
- } while (val != MACACCESS_CMD_IDLE && timeout--);
-
- if (!timeout)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int ocelot_mac_table_add(struct ocelot_private *priv,
- const unsigned char mac[ETH_ALEN], int pgid)
-{
- u32 macl = 0, mach = 0;
- int ret;
-
- /* Set the MAC address to handle and the vlan associated in a format
- * understood by the hardware.
- */
- mach |= MAC_VID << 16;
- mach |= ((u32)mac[0]) << 8;
- mach |= ((u32)mac[1]) << 0;
- macl |= ((u32)mac[2]) << 24;
- macl |= ((u32)mac[3]) << 16;
- macl |= ((u32)mac[4]) << 8;
- macl |= ((u32)mac[5]) << 0;
-
- writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
- writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
-
- writel(ANA_TABLES_MACACCESS_VALID |
- ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
- ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
- ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
- priv->regs[ANA] + ANA_TABLES_MACACCESS);
-
- ret = ocelot_vlant_wait_for_completion(priv);
-
- return ret;
-}
-
static int ocelot_write_hwaddr(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
- ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
static int ocelot_start(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
0xff };
int ret;
return ret;
/* Set MAC address tables entries for CPU redirection */
- ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
+ PGID_BROADCAST);
writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
/* It should be setup latter in ocelot_write_hwaddr */
- ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+ mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
struct ocelot_private *priv = dev_get_priv(dev);
u32 ifh[IFH_LEN];
int port = BIT(0); /* use port 0 */
- u8 grp = 0; /* Send everything on CPU group 0 */
- int i, count = (length + 3) / 4, last = length % 4;
u32 *buf = packet;
- writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
- priv->regs[QS] + QS_INJ_CTRL(grp));
-
/*
* Generate the IFH for frame injection
*
ifh[2] = (0xff & port) << 24;
ifh[3] = (IFH_TAG_TYPE_C << 16);
- for (i = 0; i < IFH_LEN; i++)
- writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
-
- for (i = 0; i < count; i++)
- writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
-
- /* Add padding */
- while (i < (OCELOT_BUF_CELL_SZ / 4)) {
- writel(0, priv->regs[QS] + QS_INJ_WR(grp));
- i++;
- }
-
- /* Indicate EOF and valid bytes in last word */
- writel(QS_INJ_CTRL_GAP_SIZE(1) |
- QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
- QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
-
- /* Add dummy CRC */
- writel(0, priv->regs[QS] + QS_INJ_WR(grp));
-
- return 0;
+ return mscc_send(priv->regs[QS], ocelot_regs_qs,
+ ifh, IFH_LEN, buf, length);
}
static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct ocelot_private *priv = dev_get_priv(dev);
- u8 grp = 0; /* Send everything on CPU group 0 */
u32 *rxbuf = (u32 *)net_rx_packets[0];
- int i, byte_cnt = 0;
- bool eof_flag = false, pruned_flag = false, abort_flag = false;
-
- if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
- return -EAGAIN;
-
- /* skip IFH */
- for (i = 0; i < IFH_LEN; i++)
- readl(priv->regs[QS] + QS_XTR_RD(grp));
-
- while (!eof_flag) {
- u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
-
- switch (val) {
- case XTR_NOT_READY:
- debug("%d NOT_READY...?\n", byte_cnt);
- break;
- case XTR_ABORT:
- /* really nedeed?? not done in linux */
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- abort_flag = true;
- eof_flag = true;
- debug("XTR_ABORT\n");
- break;
- case XTR_EOF_0:
- case XTR_EOF_1:
- case XTR_EOF_2:
- case XTR_EOF_3:
- byte_cnt += XTR_VALID_BYTES(val);
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- eof_flag = true;
- debug("EOF\n");
- break;
- case XTR_PRUNED:
- /* But get the last 4 bytes as well */
- eof_flag = true;
- pruned_flag = true;
- debug("PRUNED\n");
- /* fallthrough */
- case XTR_ESCAPE:
- *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
- byte_cnt += 4;
- rxbuf++;
- debug("ESCAPED\n");
- break;
- default:
- *rxbuf = val;
- byte_cnt += 4;
- rxbuf++;
- }
- }
+ int byte_cnt;
- if (abort_flag || pruned_flag || !eof_flag) {
- debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
- abort_flag, pruned_flag, eof_flag);
- return -EAGAIN;
- }
+ byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
+ false);
*packetp = net_rx_packets[0];
return byte_cnt;
}
+static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
+{
+ int i = 0;
+
+ for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i)
+ if (miim[i].miim_base == base && miim[i].miim_size == size)
+ return miim[i].bus;
+
+ return NULL;
+}
+
+static void add_port_entry(struct ocelot_private *priv, size_t index,
+ size_t phy_addr, struct mii_dev *bus,
+ u8 serdes_index, u8 phy_mode)
+{
+ priv->ports[index].phy_addr = phy_addr;
+ priv->ports[index].bus = bus;
+ priv->ports[index].serdes_index = serdes_index;
+ priv->ports[index].phy_mode = phy_mode;
+}
+
+static int external_bus(struct ocelot_private *priv, size_t port_index)
+{
+ return priv->ports[port_index].serdes_index != 0xff;
+}
+
static int ocelot_probe(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- int ret, i;
+ int i, ret;
+ struct resource res;
+ phys_addr_t addr_base;
+ unsigned long addr_size;
+ ofnode eth_node, node, mdio_node;
+ size_t phy_addr;
+ struct mii_dev *bus;
+ struct ofnode_phandle_args phandle;
+ struct phy_device *phy;
- struct {
- enum ocelot_target id;
- char *name;
- } reg[] = {
- { SYS, "sys" },
- { REW, "rew" },
- { QSYS, "qsys" },
- { ANA, "ana" },
- { QS, "qs" },
- { HSIO, "hsio" },
- { PORT0, "port0" },
- { PORT1, "port1" },
- { PORT2, "port2" },
- { PORT3, "port3" },
- };
-
- for (i = 0; i < ARRAY_SIZE(reg); i++) {
- priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
- if (!priv->regs[reg[i].id]) {
- pr_err
- ("Error %d: can't get regs base addresses for %s\n",
- ret, reg[i].name);
+ if (!priv)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
+ priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
+ if (!priv->regs[i]) {
+ debug
+ ("Error can't get regs base addresses for %s\n",
+ regs_names[i]);
return -ENOMEM;
}
}
- priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+ /* Initialize miim buses */
+ memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
+ OCELOT_MIIM_BUS_COUNT);
+
+ /* iterate all the ports and find out on which bus they are */
+ i = 0;
+ eth_node = dev_read_first_subnode(dev);
+ for (node = ofnode_first_subnode(eth_node); ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ if (ofnode_read_resource(node, 0, &res))
+ return -ENOMEM;
+ i = res.start;
+
+ ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
+ &phandle);
+
+ /* Get phy address on mdio bus */
+ if (ofnode_read_resource(phandle.node, 0, &res))
+ return -ENOMEM;
+ phy_addr = res.start;
+
+ /* Get mdio node */
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ if (ofnode_read_resource(mdio_node, 0, &res))
+ return -ENOMEM;
+
+ addr_base = res.start;
+ addr_size = res.end - res.start;
+
+ /* If the bus is new then create a new bus */
+ if (!get_mdiobus(addr_base, addr_size))
+ priv->bus[miim_count] =
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
+
+ /* Connect mdio bus with the port */
+ bus = get_mdiobus(addr_base, addr_size);
+
+ /* Get serdes info */
+ ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
+ 3, 0, &phandle);
+ if (ret)
+ add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
+ else
+ add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
+ phandle.args[2]);
+ }
+
+ mscc_phy_reset();
+
+ for (i = 0; i < MAX_PORT; i++) {
+ if (!priv->ports[i].bus)
+ continue;
- for (i = 0; i < 4; i++) {
- phy_connect(priv->bus[INTERNAL], i, dev,
- PHY_INTERFACE_MODE_NONE);
+ phy = phy_connect(priv->ports[i].bus,
+ priv->ports[i].phy_addr, dev,
+ PHY_INTERFACE_MODE_NONE);
+ if (phy && external_bus(priv, i))
+ board_phy_config(phy);
}
return 0;
struct ocelot_private *priv = dev_get_priv(dev);
int i;
- for (i = 0; i < NUM_PHY; i++) {
+ for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) {
mdio_unregister(priv->bus[i]);
mdio_free(priv->bus[i]);
}
.probe = ocelot_probe,
.remove = ocelot_remove,
.ops = &ocelot_ops,
- .priv_auto_alloc_size = sizeof(struct ocelot_private),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct ocelot_private),
+ .plat_auto = sizeof(struct eth_pdata),
};
projects / platform / kernel / u-boot.git / blobdiff