Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

[platform/kernel/linux-starfive.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_err.h

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
index e0e3b58..51a7d4e 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
@@ -7,9 +7,11 @@
 #include "hclge_main.h"
 
 #define HCLGE_RAS_PF_OTHER_INT_STS_REG   0x20B00
-#define HCLGE_RAS_REG_FE_MASK    0xFF
 #define HCLGE_RAS_REG_NFE_MASK   0xFF00
-#define HCLGE_RAS_REG_NFE_SHIFT        8
+#define HCLGE_RAS_REG_ROCEE_ERR_MASK   0x3000000
+
+#define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG   0x20800
+#define HCLGE_VECTOR0_REG_MSIX_MASK   0x1FF00
 
 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN   0xFFFF0000
 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK      0xFFFF0000
@@ -23,6 +25,8 @@
 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK    0x0100
 #define HCLGE_TQP_ECC_ERR_INT_EN       0x0FFF
 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK  0x0FFF
+#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK    0x0F000000
+#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
 #define HCLGE_IGU_ERR_INT_EN   0x0000066F
 #define HCLGE_IGU_ERR_INT_EN_MASK      0x000F
 #define HCLGE_IGU_TNL_ERR_INT_EN    0x0002AABF
@@ -41,21 +45,55 @@
 #define HCLGE_TM_QCN_MEM_ERR_INT_EN    0xFFFFFF
 #define HCLGE_NCSI_ERR_INT_EN  0x3
 #define HCLGE_NCSI_ERR_INT_TYPE        0x9
+#define HCLGE_MAC_COMMON_ERR_INT_EN            GENMASK(7, 0)
+#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK       GENMASK(7, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN         GENMASK(31, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK    GENMASK(31, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN         GENMASK(31, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK    GENMASK(31, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN         0x3FFF3FFF
+#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK    0x3FFF3FFF
+#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2                0xB
+#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK   0xB
+#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN         GENMASK(7, 0)
+#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK    GENMASK(23, 16)
+#define HCLGE_PPU_PF_ABNORMAL_INT_EN           GENMASK(5, 0)
+#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK      GENMASK(5, 0)
+#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN          GENMASK(31, 0)
+#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK     GENMASK(31, 0)
+#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN     GENMASK(31, 0)
+#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK        GENMASK(31, 0)
+#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN         0x0101
+#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK    0x0101
+#define HCLGE_SSU_COMMON_INT_EN                        GENMASK(9, 0)
+#define HCLGE_SSU_COMMON_INT_EN_MASK           GENMASK(9, 0)
+#define HCLGE_SSU_PORT_BASED_ERR_INT_EN                0x0BFF
+#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK   0x0BFF0000
+#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN     GENMASK(23, 0)
+#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK        GENMASK(23, 0)
+
+#define HCLGE_SSU_COMMON_ERR_INT_MASK  GENMASK(9, 0)
+#define HCLGE_SSU_PORT_INT_MSIX_MASK   0x7BFF
+#define HCLGE_IGU_INT_MASK             GENMASK(3, 0)
+#define HCLGE_IGU_EGU_TNL_INT_MASK     GENMASK(5, 0)
+#define HCLGE_PPP_MPF_INT_ST3_MASK     GENMASK(5, 0)
+#define HCLGE_PPU_MPF_INT_ST3_MASK     GENMASK(7, 0)
+#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK        GENMASK(29, 28)
+#define HCLGE_PPU_PF_INT_MSIX_MASK     0x27
+#define HCLGE_QCN_FIFO_INT_MASK                GENMASK(17, 0)
+#define HCLGE_QCN_ECC_INT_MASK         GENMASK(21, 0)
+#define HCLGE_NCSI_ECC_INT_MASK                GENMASK(1, 0)
 
-#define HCLGE_IMP_TCM_ECC_INT_MASK     0xFFFF
-#define HCLGE_IMP_ITCM4_ECC_INT_MASK   0x3
-#define HCLGE_CMDQ_ECC_INT_MASK                0xFFFF
-#define HCLGE_CMDQ_ROC_ECC_INT_SHIFT   16
-#define HCLGE_TQP_ECC_INT_MASK         0xFFF
-#define HCLGE_TQP_ECC_INT_SHIFT                16
-#define HCLGE_IMP_TCM_ECC_CLR_MASK     0xFFFF
-#define HCLGE_IMP_ITCM4_ECC_CLR_MASK   0x3
-#define HCLGE_CMDQ_NIC_ECC_CLR_MASK    0xFFFF
-#define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK  0xFFFF0000
-#define HCLGE_TQP_IMP_ERR_CLR_MASK     0x0FFF0001
-#define HCLGE_IGU_COM_INT_MASK         0xF
-#define HCLGE_IGU_EGU_TNL_INT_MASK     0x3F
-#define HCLGE_PPP_PF_INT_MASK          0x100
+#define HCLGE_ROCEE_RAS_NFE_INT_EN             0xF
+#define HCLGE_ROCEE_RAS_CE_INT_EN              0x1
+#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK                0xF
+#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK         0x1
+#define HCLGE_ROCEE_RERR_INT_MASK              BIT(0)
+#define HCLGE_ROCEE_BERR_INT_MASK              BIT(1)
+#define HCLGE_ROCEE_ECC_INT_MASK               BIT(2)
+#define HCLGE_ROCEE_OVF_INT_MASK               BIT(3)
+#define HCLGE_ROCEE_OVF_ERR_INT_MASK           0x10000
+#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK          0x3F
 
 enum hclge_err_int_type {
        HCLGE_ERR_INT_MSIX = 0,
@@ -67,9 +105,7 @@ enum hclge_err_int_type {
 struct hclge_hw_blk {
        u32 msk;
        const char *name;
-       int (*enable_error)(struct hclge_dev *hdev, bool en);
-       void (*process_error)(struct hclge_dev *hdev,
-                             enum hclge_err_int_type type);
+       int (*config_err_int)(struct hclge_dev *hdev, bool en);
 };
 
 struct hclge_hw_error {
@@ -78,6 +114,7 @@ struct hclge_hw_error {
 };
 
 int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
-int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en);
-pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
+pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
+int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
+                              unsigned long *reset_requests);
 #endif