#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
TOTAL_DESC * DMA_DESC_SIZE)
+static bool skip_umac_reset = true;
+module_param(skip_umac_reset, bool, 0444);
+MODULE_PARM_DESC(skip_umac_reset, "Skip UMAC reset step");
+
static inline void bcmgenet_writel(u32 value, void __iomem *offset)
{
/* MIPS chips strapped for BE will automagically configure the
bcmgenet_rbuf_ctrl_set(priv, 0);
udelay(10);
+ if (skip_umac_reset) {
+ pr_warn("Skipping UMAC reset\n");
+ return;
+ }
+
/* disable MAC while updating its registers */
bcmgenet_umac_writel(priv, 0, UMAC_CMD);
bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
- bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
+ bcmgenet_tdma_ring_writel(priv, index, 10, DMA_MBUF_DONE_THRESH);
/* Disable rate control for now */
bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
TDMA_FLOW_PERIOD);
netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
/* Set default coalescing parameters */
- for (i = 0; i < priv->hw_params->rx_queues; i++)
+ for (i = 0; i < priv->hw_params->rx_queues; i++) {
priv->rx_rings[i].rx_max_coalesced_frames = 1;
+ priv->rx_rings[i].rx_coalesce_usecs = 50;
+ }
priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
+ priv->rx_rings[DESC_INDEX].rx_coalesce_usecs = 50;
/* libphy will determine the link state */
netif_carrier_off(dev);