Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / drivers / net / designware.c

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 9207324..4fa26ab 100644 (file)
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2010
  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -16,14 +15,14 @@
 #include <miiphy.h>
 #include <malloc.h>
 #include <pci.h>
+#include <reset.h>
 #include <linux/compiler.h>
 #include <linux/err.h>
+#include <linux/kernel.h>
 #include <asm/io.h>
 #include <power/regulator.h>
 #include "designware.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
 #ifdef CONFIG_DM_ETH
@@ -282,6 +281,15 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
 
        writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
+       /*
+        * When a MII PHY is used, we must set the PS bit for the DMA
+        * reset to succeed.
+        */
+       if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
+               writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
+       else
+               writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
+
        start = get_timer(0);
        while (readl(&dma_p->busmode) & DMAMAC_SRST) {
                if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
@@ -344,6 +352,8 @@ int designware_eth_enable(struct dw_eth_dev *priv)
        return 0;
 }
 
+#define ETH_ZLEN       60
+
 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 {
        struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -370,6 +380,8 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
                return -EPERM;
        }
 
+       length = max(length, ETH_ZLEN);
+
        memcpy((void *)data_start, packet, length);
 
        /* Flush data to be sent */
@@ -662,6 +674,7 @@ int designware_eth_probe(struct udevice *dev)
        u32 iobase = pdata->iobase;
        ulong ioaddr;
        int ret;
+       struct reset_ctl_bulk reset_bulk;
 #ifdef CONFIG_CLK
        int i, err, clock_nb;
 
@@ -679,7 +692,7 @@ int designware_eth_probe(struct udevice *dev)
                                break;
 
                        err = clk_enable(&priv->clocks[i]);
-                       if (err) {
+                       if (err && err != -ENOSYS && err != -ENOTSUPP) {
                                pr_err("failed to enable clock %d\n", i);
                                clk_free(&priv->clocks[i]);
                                goto clk_err;
@@ -708,6 +721,12 @@ int designware_eth_probe(struct udevice *dev)
        }
 #endif
 
+       ret = reset_get_bulk(dev, &reset_bulk);
+       if (ret)
+               dev_warn(dev, "Can't get reset: %d\n", ret);
+       else
+               reset_deassert_bulk(&reset_bulk);
+
 #ifdef CONFIG_DM_PCI
        /*
         * If we are on PCI bus, either directly attached to a PCI root port,
@@ -819,6 +838,8 @@ static const struct udevice_id designware_eth_ids[] = {
        { .compatible = "altr,socfpga-stmmac" },
        { .compatible = "amlogic,meson6-dwmac" },
        { .compatible = "amlogic,meson-gx-dwmac" },
+       { .compatible = "amlogic,meson-gxbb-dwmac" },
+       { .compatible = "amlogic,meson-axg-dwmac" },
        { .compatible = "st,stm32-dwmac" },
        { }
 };