Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

[platform/kernel/linux-starfive.git] / drivers / net / can / xilinx_can.c

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index e179d31..0de2f97 100644 (file)
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /* Xilinx CAN device driver
  *
- * Copyright (C) 2012 - 2014 Xilinx, Inc.
+ * Copyright (C) 2012 - 2022 Xilinx, Inc.
  * Copyright (C) 2009 PetaLogix. All rights reserved.
  * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
  *
@@ -9,6 +9,7 @@
  * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/errno.h>
 #include <linux/init.h>
@@ -50,7 +51,7 @@ enum xcan_reg {
 
        /* only on CAN FD cores */
        XCAN_F_BRPR_OFFSET      = 0x088, /* Data Phase Baud Rate
-                                         * Prescalar
+                                         * Prescaler
                                          */
        XCAN_F_BTR_OFFSET       = 0x08C, /* Data Phase Bit Timing */
        XCAN_TRR_OFFSET         = 0x0090, /* TX Buffer Ready Request */
@@ -86,6 +87,8 @@ enum xcan_reg {
 #define XCAN_MSR_LBACK_MASK            0x00000002 /* Loop back mode select */
 #define XCAN_MSR_SLEEP_MASK            0x00000001 /* Sleep mode select */
 #define XCAN_BRPR_BRP_MASK             0x000000FF /* Baud rate prescaler */
+#define XCAN_BRPR_TDCO_MASK            GENMASK(12, 8)  /* TDCO */
+#define XCAN_2_BRPR_TDCO_MASK          GENMASK(13, 8)  /* TDCO for CANFD 2.0 */
 #define XCAN_BTR_SJW_MASK              0x00000180 /* Synchronous jump width */
 #define XCAN_BTR_TS2_MASK              0x00000070 /* Time segment 2 */
 #define XCAN_BTR_TS1_MASK              0x0000000F /* Time segment 1 */
@@ -99,6 +102,7 @@ enum xcan_reg {
 #define XCAN_ESR_STER_MASK             0x00000004 /* Stuff error */
 #define XCAN_ESR_FMER_MASK             0x00000002 /* Form error */
 #define XCAN_ESR_CRCER_MASK            0x00000001 /* CRC error */
+#define XCAN_SR_TDCV_MASK              GENMASK(22, 16) /* TDCV Value */
 #define XCAN_SR_TXFLL_MASK             0x00000400 /* TX FIFO is full */
 #define XCAN_SR_ESTAT_MASK             0x00000180 /* Error status */
 #define XCAN_SR_ERRWRN_MASK            0x00000040 /* Error warning */
@@ -132,6 +136,7 @@ enum xcan_reg {
 #define XCAN_DLCR_BRS_MASK             0x04000000 /* BRS Mask in DLC */
 
 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
+#define XCAN_BRPR_TDC_ENABLE           BIT(16) /* Transmitter Delay Compensation (TDC) Enable */
 #define XCAN_BTR_SJW_SHIFT             7  /* Synchronous jump width */
 #define XCAN_BTR_TS2_SHIFT             4  /* Time segment 2 */
 #define XCAN_BTR_SJW_SHIFT_CANFD       16 /* Synchronous jump width */
@@ -276,6 +281,26 @@ static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
        .brp_inc = 1,
 };
 
+/* Transmission Delay Compensation constants for CANFD 1.0 */
+static const struct can_tdc_const xcan_tdc_const_canfd = {
+       .tdcv_min = 0,
+       .tdcv_max = 0, /* Manual mode not supported. */
+       .tdco_min = 0,
+       .tdco_max = 32,
+       .tdcf_min = 0, /* Filter window not supported */
+       .tdcf_max = 0,
+};
+
+/* Transmission Delay Compensation constants for CANFD 2.0 */
+static const struct can_tdc_const xcan_tdc_const_canfd2 = {
+       .tdcv_min = 0,
+       .tdcv_max = 0, /* Manual mode not supported. */
+       .tdco_min = 0,
+       .tdco_max = 64,
+       .tdcf_min = 0, /* Filter window not supported */
+       .tdcf_max = 0,
+};
+
 /**
  * xcan_write_reg_le - Write a value to the device register little endian
  * @priv:      Driver private data structure
@@ -405,7 +430,7 @@ static int xcan_set_bittiming(struct net_device *ndev)
                return -EPERM;
        }
 
-       /* Setting Baud Rate prescalar value in BRPR Register */
+       /* Setting Baud Rate prescaler value in BRPR Register */
        btr0 = (bt->brp - 1);
 
        /* Setting Time Segment 1 in BTR Register */
@@ -422,8 +447,16 @@ static int xcan_set_bittiming(struct net_device *ndev)
 
        if (priv->devtype.cantype == XAXI_CANFD ||
            priv->devtype.cantype == XAXI_CANFD_2_0) {
-               /* Setting Baud Rate prescalar value in F_BRPR Register */
+               /* Setting Baud Rate prescaler value in F_BRPR Register */
                btr0 = dbt->brp - 1;
+               if (can_tdc_is_enabled(&priv->can)) {
+                       if (priv->devtype.cantype == XAXI_CANFD)
+                               btr0 |= FIELD_PREP(XCAN_BRPR_TDCO_MASK, priv->can.tdc.tdco) |
+                                       XCAN_BRPR_TDC_ENABLE;
+                       else
+                               btr0 |= FIELD_PREP(XCAN_2_BRPR_TDCO_MASK, priv->can.tdc.tdco) |
+                                       XCAN_BRPR_TDC_ENABLE;
+               }
 
                /* Setting Time Segment 1 in BTR Register */
                btr1 = dbt->prop_seg + dbt->phase_seg1 - 1;
@@ -1483,6 +1516,22 @@ static int xcan_get_berr_counter(const struct net_device *ndev,
        return 0;
 }
 
+/**
+ * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value
+ * @ndev:      Pointer to net_device structure
+ * @tdcv:      Pointer to TDCV value
+ *
+ * Return: 0 on success
+ */
+static int xcan_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv)
+{
+       struct xcan_priv *priv = netdev_priv(ndev);
+
+       *tdcv = FIELD_GET(XCAN_SR_TDCV_MASK, priv->read_reg(priv, XCAN_SR_OFFSET));
+
+       return 0;
+}
+
 static const struct net_device_ops xcan_netdev_ops = {
        .ndo_open       = xcan_open,
        .ndo_stop       = xcan_close,
@@ -1735,17 +1784,24 @@ static int xcan_probe(struct platform_device *pdev)
        priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
                                        CAN_CTRLMODE_BERR_REPORTING;
 
-       if (devtype->cantype == XAXI_CANFD)
+       if (devtype->cantype == XAXI_CANFD) {
                priv->can.data_bittiming_const =
                        &xcan_data_bittiming_const_canfd;
+               priv->can.tdc_const = &xcan_tdc_const_canfd;
+       }
 
-       if (devtype->cantype == XAXI_CANFD_2_0)
+       if (devtype->cantype == XAXI_CANFD_2_0) {
                priv->can.data_bittiming_const =
                        &xcan_data_bittiming_const_canfd2;
+               priv->can.tdc_const = &xcan_tdc_const_canfd2;
+       }
 
        if (devtype->cantype == XAXI_CANFD ||
-           devtype->cantype == XAXI_CANFD_2_0)
-               priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
+           devtype->cantype == XAXI_CANFD_2_0) {
+               priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
+                                               CAN_CTRLMODE_TDC_AUTO;
+               priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv;
+       }
 
        priv->reg_base = addr;
        priv->tx_max = tx_max;