Blackfin: bfin_mac: update port muxing

[platform/kernel/u-boot.git] / drivers / net / bfin_mac.c

diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index afe122a..dddbb78 100644 (file)
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <config.h>
 #include <net.h>
+#include <netdev.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -35,7 +36,7 @@
 #define TXBUF_BASE_ADDR                0xFF800000
 #define TX_BUF_CNT             1
 
-#define TOUT_LOOP              1000000
+#define TOUT_LOOP              1000000
 
 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
 ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
@@ -88,7 +89,7 @@ int bfin_EMAC_initialize(bd_t *bis)
 
        eth_register(dev);
 
-       return 1;
+       return 0;
 }
 
 static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
@@ -330,20 +331,43 @@ static int SetupSystemRegs(int *opmode)
        *pVR_CTL |= CLKBUFOE;
        /* Set all the pins to peripheral mode */
 
-#ifndef CONFIG_BFIN_MAC_RMII
-       *pPORTH_FER = 0xFFFF;
-#ifdef __ADSPBF52x__
-       *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
-#endif
+#ifdef CONFIG_BFIN_MAC_RMII
+       /* grab RMII pins */
+# if defined(__ADSPBF51x__)
+       *pPORTF_MUX = (*pPORTF_MUX & \
+               ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
+               PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
+       *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
+       *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
+       *pPORTG_FER |= PG0 | PG1 | PG2;
+# elif defined(__ADSPBF52x__)
+       *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
+       *pPORTG_FER |= PG14 | PG15;
+       *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
+               PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
+       *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
+# else
+       *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
+# endif
 #else
-#if defined(__ADSPBF536__) || defined(__ADSPBF537__)
-       *pPORTH_FER = 0xC373;
-#endif
-#ifdef __ADSPBF52x__
-       *pPORTH_FER = 0x01FF;
-       *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
-#endif
+       /* grab MII & RMII pins */
+# if defined(__ADSPBF51x__)
+       *pPORTF_MUX = (*pPORTF_MUX & \
+               ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
+               PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
+       *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
+       *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
+       *pPORTG_FER |= PG0 | PG1 | PG2;
+# elif defined(__ADSPBF52x__)
+       *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
+       *pPORTG_FER |= PG14 | PG15;
+       *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
+       *pPORTH_FER = -1; /* all pins */
+# else
+       *pPORTH_FER = -1; /* all pins */
+# endif
 #endif
+
        /* MDC  = 2.5 MHz */
        sysctl = SET_MDCDIV(24);
        /* Odd word alignment for Receive Frame DMA word */
@@ -465,7 +489,7 @@ ADI_ETHER_BUFFER *SetupTxBuffer(int no)
        return buf;
 }
 
-#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
 int ether_post_test(int flags)
 {
        uchar buf[64];