#include <common.h>
#include <log.h>
+#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <nand.h>
#include <dm/uclass.h>
#define NAND_TIMEOUT 10240
#define NAND_ECC_BUSY 0xC
#define NAND_4BITECC_MASK 0x03FF03FF
-#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
+#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
#define ECC_STATE_NO_ERR 0x0
#define ECC_STATE_TOO_MANY_ERRS 0x1
#define ECC_STATE_ERR_CORR_COMP_P 0x2
u_int32_t ecc = 0;
ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ CFG_SYS_NAND_CS - 2]));
return ecc;
}
nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
};
#ifdef CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
+#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11)
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
-#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
+#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12)
#endif
/**
struct nand_ecclayout *saved_ecc_layout;
/* save current ECC layout and assign Keystone RBL ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
saved_ecc_layout = chip->ecc.layout;
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail;
err:
/* restore ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail;
}
struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
/* save current ECC layout and assign Keystone RBL ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
mtd->oobavail = chip->ecc.layout->oobavail;
}
}
/* restore ECC layout */
- if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ if (page < KEYSTONE_NAND_MAX_RBL_PAGE) {
chip->ecc.layout = saved_ecc_layout;
mtd->oobavail = saved_ecc_layout->oobavail;
}
*/
val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
__raw_writel(val, &davinci_emif_regs->nandfcr);
break;
nand->ecc.calculate = nand_davinci_calculate_ecc;
nand->ecc.correct = nand_davinci_correct_data;
nand->ecc.hwctl = nand_davinci_enable_hwecc;
-#else
- nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
nand->ecc.size = 512;
nand->ecc.bytes = 10;
nand->ecc.correct = nand_davinci_4bit_correct_data;
nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
+#elif defined(CONFIG_SYS_NAND_SOFT_ECC)
+ nand->ecc.mode = NAND_ECC_SOFT;
#endif
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
nand->dev_ready = nand_davinci_dev_ready;
}
-#ifdef CONFIG_SYS_NAND_SELF_INIT
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static int davinci_nand_probe(struct udevice *dev)
{
struct nand_chip *nand = dev_get_priv(dev);
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
- nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
davinci_nand_init(nand);