This option, if enabled, provides more flexible and linux-like
NAND initialization process.
-config SYS_NAND_DRIVER_ECC_LAYOUT
+config SPL_SYS_NAND_SELF_INIT
+ bool
+ depends on !SPL_NAND_SIMPLE
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process, in SPL.
+
+config TPL_SYS_NAND_SELF_INIT
bool
+ depends on TPL_NAND_SUPPORT
help
- Omit standard ECC layouts to safe space. Select this if your driver
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process, in SPL.
+
+config TPL_NAND_INIT
+ bool
+
+config SYS_MAX_NAND_DEVICE
+ int "Maximum number of NAND devices to support"
+ default 1
+
+config SYS_NAND_DRIVER_ECC_LAYOUT
+ bool "Omit standard ECC layouts to save space"
+ help
+ Omit standard ECC layouts to save space. Select this if your driver
is known to provide its own ECC layout.
config SYS_NAND_USE_FLASH_BBT
config NAND_ATMEL
bool "Support Atmel NAND controller"
+ select SYS_NAND_SELF_INIT
imply SYS_NAND_USE_FLASH_BBT
help
Enable this driver for NAND flash platforms using an Atmel NAND
config ATMEL_NAND_HWECC
bool "Atmel Hardware ECC"
- default n
config ATMEL_NAND_HW_PMECC
bool "Atmel Programmable Multibit ECC (PMECC)"
select ATMEL_NAND_HWECC
- default n
help
The Programmable Multibit ECC (PMECC) controller is a programmable
binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
config SPL_GENERATE_ATMEL_PMECC_HEADER
bool "Atmel PMECC Header Generation"
+ depends on SPL
select ATMEL_NAND_HWECC
select ATMEL_NAND_HW_PMECC
- default n
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.
config NAND_BRCMNAND
bool "Support Broadcom NAND controller"
depends on OF_CONTROL && DM && DM_MTD
+ select SYS_NAND_SELF_INIT
help
Enable the driver for NAND flash on platforms using a Broadcom NAND
controller.
help
Enable support for broadcom nand driver on bcm6368.
+config NAND_BRCMNAND_6753
+ bool "Support Broadcom NAND controller on bcm6753"
+ depends on NAND_BRCMNAND && BCM6855
+ help
+ Enable support for broadcom nand driver on bcm6753.
+
config NAND_BRCMNAND_68360
bool "Support Broadcom NAND controller on bcm68360"
- depends on NAND_BRCMNAND && ARCH_BCM68360
+ depends on NAND_BRCMNAND && BCM6856
help
Enable support for broadcom nand driver on bcm68360.
config NAND_BRCMNAND_6858
bool "Support Broadcom NAND controller on bcm6858"
- depends on NAND_BRCMNAND && ARCH_BCM6858
+ depends on NAND_BRCMNAND && BCM6858
help
Enable support for broadcom nand driver on bcm6858.
config NAND_BRCMNAND_63158
bool "Support Broadcom NAND controller on bcm63158"
- depends on NAND_BRCMNAND && ARCH_BCM63158
+ depends on NAND_BRCMNAND && BCM63158
help
Enable support for broadcom nand driver on bcm63158.
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
+ select SYS_NAND_SELF_INIT if TARGET_DA850EVM
help
Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms
+config SYS_NAND_4BIT_HW_ECC_OOBFIRST
+ bool "Use 4-bit HW ECC with OOB at the front"
+ depends on NAND_DAVINCI
+
+config KEYSTONE_RBL_NAND
+ depends on ARCH_KEYSTONE
+ def_bool y
+
+config SPL_NAND_LOAD
+ def_bool y
+ depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
+
config NAND_DENALI
bool
select SYS_NAND_SELF_INIT
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
+config NAND_FSL_ELBC
+ bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
+ select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
+ select SPL_SYS_NAND_SELF_INIT
+ select SYS_NAND_SELF_INIT
+ depends on FSL_ELBC
+ help
+ Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
+
+config NAND_FSL_ELBC_DT
+ bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
+ depends on NAND_FSL_ELBC
+
+config NAND_FSL_IFC
+ bool "Support Freescale Integrated Flash Controller NAND driver"
+ select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
+ select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
+ select SPL_SYS_NAND_SELF_INIT
+ select SYS_NAND_SELF_INIT
+ select FSL_IFC
+ help
+ Enable the Freescale Integrated Flash Controller NAND driver.
+
+config NAND_LPC32XX_MLC
+ bool "Support LPC32XX_MLC controller"
+ select SYS_NAND_SELF_INIT
+ help
+ Enable the LPC32XX MLC NAND controller.
+
config NAND_LPC32XX_SLC
bool "Support LPC32XX_SLC controller"
help
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
and BCH16 ECC algorithms.
+if NAND_OMAP_GPMC
+
config NAND_OMAP_GPMC_PREFETCH
bool "Enable GPMC Prefetch"
- depends on NAND_OMAP_GPMC
default y
help
On OMAP platforms that use the GPMC controller
config NAND_OMAP_ELM
bool "Enable ELM driver for OMAPxx and AMxx platforms."
- depends on NAND_OMAP_GPMC && !OMAP34XX
+ depends on !OMAP34XX
help
ELM controller is used for ECC error detection (not ECC calculation)
of BCH4, BCH8 and BCH16 ECC algorithms.
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
+choice
+ prompt "ECC scheme"
+ default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ help
+ On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+ It can take following values:
+ OMAP_ECC_HAM1_CODE_SW
+ 1-bit Hamming code using software lib.
+ (for legacy devices only)
+ OMAP_ECC_HAM1_CODE_HW
+ 1-bit Hamming code using GPMC hardware.
+ (for legacy devices only)
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH4_CODE_HW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using software library.
+ - requires CONFIG_BCH to enable software BCH library
+ (For legacy device which do not have ELM h/w engine)
+ OMAP_ECC_BCH8_CODE_HW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+ OMAP_ECC_BCH16_CODE_HW
+ 16-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+ How to select ECC scheme on OMAP and AMxx platforms ?
+ -----------------------------------------------------
+ Though higher ECC schemes have more capability to detect and correct
+ bit-flips, but still selection of ECC scheme is dependent on following
+ - hardware engines present in SoC.
+ Some legacy OMAP SoC do not have ELM h/w engine thus such
+ SoC cannot support BCHx_HW ECC schemes.
+ - size of OOB/Spare region
+ With higher ECC schemes, more OOB/Spare area is required to
+ store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+ In general following expression can help:
+ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+ where
+ NAND_OOBSIZE = number of bytes available in
+ OOB/spare area per NAND page.
+ NAND_PAGESIZE = bytes in main-area of NAND page.
+ ECC_BYTES = number of ECC bytes generated to
+ protect 512 bytes of data, which is:
+ 3 for HAM1_xx ecc schemes
+ 7 for BCH4_xx ecc schemes
+ 14 for BCH8_xx ecc schemes
+ 26 for BCH16_xx ecc schemes
+
+ example to check for BCH16 on 2K page NAND
+ NAND_PAGESIZE = 2048
+ NAND_OOBSIZE = 64
+ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+ Thus BCH16 cannot be supported on 2K page NAND.
+
+ However, for 4K pagesize NAND
+ NAND_PAGESIZE = 4096
+ NAND_OOBSIZE = 224
+ ECC_BYTES = 26
+ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+ Thus BCH16 can be supported on 4K page NAND.
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ bool "1-bit Hamming code using software lib"
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ bool "1-bit Hamming code using GPMC hardware"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ bool "8-bit BCH code with HW calculation SW error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ bool "8-bit BCH code with HW calculation and error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ bool "16-bit BCH code with HW calculation and error detection"
+
+endchoice
+
+config NAND_OMAP_ECCSCHEME
+ int
+ default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ help
+ This must be kept in sync with the enum in
+ include/linux/mtd/omap_gpmc.h
+
+endif
+
config NAND_VF610_NFC
bool "Support for Freescale NFC for VF610"
select SYS_NAND_SELF_INIT
select SYS_NAND_SELF_INIT
select SYS_NAND_U_BOOT_LOCATIONS
select SPL_NAND_SUPPORT
+ select SPL_SYS_NAND_SELF_INIT
imply CMD_NAND
---help---
Enable support for NAND. This option enables the standard and
imply CMD_NAND
help
This enables the NAND driver for the NAND flash controller on the
- i.MX27 / i.MX31 / i.MX5 rocessors.
+ i.MX27 / i.MX31 / i.MX5 processors.
config NAND_MXS
bool "MXS NAND support"
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
+ select SPL_SYS_NAND_SELF_INIT
select SYS_NAND_SELF_INIT
imply CMD_NAND
select APBH_DMA
endif
+config NAND_MXIC
+ bool "Macronix raw NAND controller"
+ select SYS_NAND_SELF_INIT
+ help
+ This selects the Macronix raw NAND controller driver.
+
config NAND_ZYNQ
bool "Support for Zynq Nand controller"
+ select SPL_SYS_NAND_SELF_INIT
select SYS_NAND_SELF_INIT
select DM_MTD
imply CMD_NAND
NFC v800: RK3308, RV1108
NFC v900: PX30, RK3326
+config TEGRA_NAND
+ bool "Support for NAND controller on Tegra SoCs"
+ depends on ARCH_TEGRA
+ select SYS_NAND_SELF_INIT
+ imply CMD_NAND
+ help
+ Enables support for NAND Flash chips on Tegra SoCs platforms.
+
+config NAND_MT7621
+ bool "Support for MediaTek MT7621 NAND flash controller"
+ depends on SOC_MT7621
+ select SYS_NAND_SELF_INIT
+ select SPL_SYS_NAND_SELF_INIT
+ imply CMD_NAND
+ help
+ This enables NAND driver for the NAND flash controller on MediaTek
+ MT7621 platform.
+ The controller supports 4~12 bits correction per 512 bytes with a
+ maximum 4KB page size.
+
comment "Generic NAND options"
config SYS_NAND_BLOCK_SIZE
hex "NAND chip eraseblock size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
+ !NAND_FSL_IFC && !NAND_MT7621
help
Number of data bytes in one eraseblock for the NAND chip on the
board. This is the multiple of NAND_PAGE_SIZE and the number of
pages.
+config SYS_NAND_ONFI_DETECTION
+ bool "Enable detection of ONFI compliant devices during probe"
+ help
+ Enables detection of ONFI compliant devices during probe.
+ And fetching device parameters flashed on device, by parsing
+ ONFI parameter page.
+
+config SYS_NAND_PAGE_COUNT
+ hex "NAND chip page count"
+ depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
+ SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
+ help
+ Number of pages in the NAND chip.
+
config SYS_NAND_PAGE_SIZE
hex "NAND chip page size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
+ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
help
Number of data bytes in one page for the NAND chip on the
board, not including the OOB area.
config SYS_NAND_OOBSIZE
hex "NAND chip OOB size"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
+ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of bytes in the Out-Of-Band area for the NAND chip on
the board.
not available while configuring controller. So a static CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
-config SYS_NAND_MAX_CHIPS
- int "NAND max chips"
- default 1
- depends on NAND_ARASAN
+if SPL
+
+config SYS_NAND_5_ADDR_CYCLE
+ bool "Wait 5 address cycles during NAND commands"
+ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
+ (SPL_NAND_SUPPORT && NAND_ATMEL)
+ default y
help
- The maximum number of NAND chips per device to be supported.
+ Some controllers require waiting for 5 address cycles when issuing
+ some commands, on NAND chips larger than 128MiB.
-if SPL
+choice
+ prompt "NAND bad block marker/indicator position in the OOB"
+ depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
+ SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
+ default HAS_NAND_LARGE_BADBLOCK_POS
+ help
+ In the OOB, which position contains the badblock information.
+
+config HAS_NAND_LARGE_BADBLOCK_POS
+ bool "Set the bad block marker/indicator to the 'large' position"
+
+config HAS_NAND_SMALL_BADBLOCK_POS
+ bool "Set the bad block marker/indicator to the 'small' position"
+
+endchoice
+
+config SYS_NAND_BAD_BLOCK_POS
+ int
+ default 0 if HAS_NAND_LARGE_BADBLOCK_POS
+ default 5 if HAS_NAND_SMALL_BADBLOCK_POS
config SYS_NAND_U_BOOT_LOCATIONS
bool "Define U-boot binaries locations in NAND"
config SPL_NAND_AM33XX_BCH
bool "Enables SPL-NAND driver which supports ELM based"
- depends on NAND_OMAP_GPMC && !OMAP34XX
+ depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
default y
help
Hardware ECC correction. This is useful for platforms which have ELM
config SPL_NAND_DENALI
bool "Support Denali NAND controller for SPL"
+ depends on SPL_NAND_SUPPORT
help
This is a small implementation of the Denali NAND controller
for use on SPL.
config SPL_NAND_SIMPLE
bool "Use simple SPL NAND driver"
- depends on !SPL_NAND_AM33XX_BCH
+ depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
help
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
projects / platform / kernel / u-boot.git / blobdiff