struct fsl_elbc_mtd *chips[MAX_BANKS];
/* device info */
- fsl_lbus_t *regs;
+ fsl_lbc_t *regs;
u8 __iomem *addr; /* Address of assigned FCM buffer */
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
long long end_tick;
u32 ltesr;
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
ctrl->use_mdr = 0;
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- fsl_lbus_t *lbc = ctrl->regs;
+ fsl_lbc_t *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
static int fsl_elbc_read_page(struct mtd_info *mtd,
struct nand_chip *chip,
- uint8_t *buf)
+ uint8_t *buf, int page)
{
fsl_elbc_read_buf(mtd, buf, mtd->writesize);
fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
if (!elbc_ctrl)
return;
-#ifdef CONFIG_MPC85xx
- elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
-#else
- elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
-#endif
+ elbc_ctrl->regs = LBC_BASE_ADDR;
/* clear event registers */
out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);